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fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… #2551

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merged 2 commits into from
Nov 24, 2024
Merged

fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… #2551

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7a36c58
fix xtensa `DecodeMR23RegisterClass` and add tests for `MAC16` instru…
imbillow Nov 23, 2024
b3561a1
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imbillow Nov 23, 2024
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4 changes: 2 additions & 2 deletions arch/Xtensa/XtensaDisassembler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -225,10 +225,10 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
if ((RegNo < 2) || (RegNo > 3))
if (RegNo >= ARR_SIZE(MR23DecoderTable))
return MCDisassembler_Fail;

unsigned Reg = MR23DecoderTable[RegNo - 2];
unsigned Reg = MR23DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
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97 changes: 97 additions & 0 deletions tests/MC/Xtensa/mac16.s.yaml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,97 @@
test_cases:
- input:
bytes: [ 0x04,0x01,0x34 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.ad.ll a1, m2"
- input:
bytes: [ 0x14,0x02,0x74 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.aa.ll a2, a1"
- input:
bytes: [ 0x14,0x00,0x64 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.da.ll m0, a1"
- input:
bytes: [ 0x04,0x00,0x24 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mul.dd.ll m0, m2"
- input:
bytes: [ 0x04,0x01,0x38 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.ad.ll a1, m2"
- input:
bytes: [ 0x14,0x02,0x78 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.aa.ll a2, a1"
- input:
bytes: [ 0x14,0x00,0x68 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.da.ll m0, a1"
- input:
bytes: [ 0x04,0x00,0x28 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.dd.ll m0, m2"
- input:
bytes: [ 0x14,0x00,0x58 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.da.ll.lddec m0, a0, m0, a1"
- input:
bytes: [ 0x14,0x00,0x48 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.da.ll.ldinc m0, a0, m0, a1"
- input:
bytes: [ 0x04,0x00,0x18 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.dd.ll.lddec m0, a0, m0, m2"
- input:
bytes: [ 0x04,0x00,0x08 ]
arch: "xtensa"
options: [ ]
address: 0x0
expected:
insns:
- asm_text: "mula.dd.ll.ldinc m0, a0, m0, m2"
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