Merge pull request Xilinx#25 from davidd/2021.1_next

Minor 2021.1 updates, fixing logos and typos
cf-herman · Apr 15, 2022 · 7eec9a1 · 7eec9a1
2 parents bdee517 + dfe99c4
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diff --git a/...cture_Tutorials/UltrascalePlus/DFX/Abstract_Shell_Per_SLR_Compilation/Readme.md b/...cture_Tutorials/UltrascalePlus/DFX/Abstract_Shell_Per_SLR_Compilation/Readme.md
diff --git a/Device_Architecture_Tutorials/UltrascalePlus/DFX/DFX_Decoupler/README.md b/Device_Architecture_Tutorials/UltrascalePlus/DFX/DFX_Decoupler/README.md
@@ -1,6 +1,6 @@
 <table>
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-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>DFX Tutorial</h1>
    </td>
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diff --git a/Device_Architecture_Tutorials/Versal/Boot_and_Config/Classic_SoC_Boot/README.md b/Device_Architecture_Tutorials/Versal/Boot_and_Config/Classic_SoC_Boot/README.md
@@ -1,6 +1,6 @@
 <table>
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-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
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diff --git a/...ce_Architecture_Tutorials/Versal/DFX/1RP_AXI_GPIO_in_RP_Interface_INI/Readme.md b/...ce_Architecture_Tutorials/Versal/DFX/1RP_AXI_GPIO_in_RP_Interface_INI/Readme.md
@@ -1,6 +1,6 @@
 <table>
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-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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diff --git a/...e_Architecture_Tutorials/Versal/DFX/2RP_GPIO_BRAM_in_RP_Interface_INI/Readme.md b/...e_Architecture_Tutorials/Versal/DFX/2RP_GPIO_BRAM_in_RP_Interface_INI/Readme.md
@@ -1,6 +1,6 @@
 <table>
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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diff --git a/Device_Architecture_Tutorials/Versal/DFX/2RPs_Sharing_ClockRegion/Readme.md b/Device_Architecture_Tutorials/Versal/DFX/2RPs_Sharing_ClockRegion/Readme.md
@@ -1,6 +1,6 @@
 <table>
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-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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diff --git a/Device_Architecture_Tutorials/Versal/DFX/Debug_JTAG_HSDP/Readme.md b/Device_Architecture_Tutorials/Versal/DFX/Debug_JTAG_HSDP/Readme.md
@@ -1,6 +1,6 @@
 <table>
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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diff --git a/Device_Architecture_Tutorials/Versal/DFX/Embedded_IOB_inside_RM/readme.md b/Device_Architecture_Tutorials/Versal/DFX/Embedded_IOB_inside_RM/readme.md
@@ -1,6 +1,6 @@
 <table>
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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diff --git a/Device_Architecture_Tutorials/Versal/DFX/NoC_INI_Static_RM_Interface/Readme.md b/Device_Architecture_Tutorials/Versal/DFX/NoC_INI_Static_RM_Interface/Readme.md
@@ -1,6 +1,6 @@
 <table>
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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diff --git a/Device_Architecture_Tutorials/Versal/DFX/Update_BD_Boundary/Readme.md b/Device_Architecture_Tutorials/Versal/DFX/Update_BD_Boundary/Readme.md
@@ -1,6 +1,6 @@
 <table>
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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diff --git a/Device_Architecture_Tutorials/Versal/DFX/VNOC_Sharing/Readme.md b/Device_Architecture_Tutorials/Versal/DFX/VNOC_Sharing/Readme.md
@@ -1,6 +1,6 @@
 <table>
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-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Versal DFX Tutorial</h1>
+   <td align="center"><img src="https://github.com/Xilinx/Image-Collateral/blob/main/xilinx-logo.png?raw=true" width="30%"/><h1>Versal DFX Tutorial</h1>
    </td>
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