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Merge pull request #79 from antmicro/use-riscv-dv
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Use RISC-V DV for core verification
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@kgugala
kgugala authored Apr 24, 2023
2 parents 43134ec + fdefb36 commit 41571a6
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254 changes: 254 additions & 0 deletions .github/workflows/riscv-dv.yml
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name: RISC-V DV tests

on:
push:
pull_request:

jobs:

verilator:
name: Build Verilator
runs-on: ubuntu-latest
env:
CCACHE_DIR: "/opt/veer-el2/.cache/"
DEBIAN_FRONTEND: "noninteractive"

steps:
- name: Install prerequisities
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git autoconf automake autotools-dev curl python3 python3-pip \
libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex \
texinfo gperf libtool patchutils bc zlib1g zlib1g-dev libexpat-dev \
ninja-build ccache libfl2 libfl-dev
- name: Create Cache Timestamp
id: cache_timestamp
uses: nanzm/[email protected]
with:
format: 'YYYY-MM-DD-HH-mm-ss'

- name: Setup cache
uses: actions/cache@v2
timeout-minutes: 3
continue-on-error: true
with:
path: "/opt/veer-el2/.cache/"
key: cache_verilator_${{ steps.cache_timestamp.outputs.time }}
restore-keys: cache_verilator_

- name: Build Verilator
run: |
git clone https://github.com/verilator/verilator
pushd verilator
git checkout v5.002
autoconf
./configure --prefix=/opt/verilator
make -j `nproc`
make install
popd
cd /opt && tar -czvf verilator.tar.gz verilator/
- name: Store Verilator binaries
uses: actions/upload-artifact@v3
with:
name: verilator
path: /opt/*.tar.gz
retention-days: 1

spike:
name: Build Spike ISS
runs-on: ubuntu-latest
env:
CCACHE_DIR: "/opt/veer-el2/.cache/"
DEBIAN_FRONTEND: "noninteractive"

steps:
- name: Install prerequisities
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git build-essential cmake ccache device-tree-compiler
- name: Create Cache Timestamp
id: cache_timestamp
uses: nanzm/[email protected]
with:
format: 'YYYY-MM-DD-HH-mm-ss'

- name: Setup cache
uses: actions/cache@v2
timeout-minutes: 3
continue-on-error: true
with:
path: "/opt/veer-el2/.cache/"
key: cache_spike_${{ steps.cache_timestamp.outputs.time }}
restore-keys: cache_spike_

- name: Build Spike
run: |
git clone https://github.com/riscv-software-src/riscv-isa-sim spike
export CC="ccache gcc"
export CXX="ccache g++"
pushd spike
git checkout d70ea67d
mkdir build
cd build
../configure --prefix=/opt/spike
make -j`nproc`
make install
popd
rm -rf /opt/spike/include # Remove include and lib to save space
rm -rf /opt/spike/lib
cd /opt && tar -czvf spike.tar.gz spike/
- name: Store Spike binaries
uses: actions/upload-artifact@v3
with:
name: spike
path: /opt/*.tar.gz
retention-days: 1

veer-iss:
name: Build VeeR-ISS
runs-on: ubuntu-latest
env:
CCACHE_DIR: "/opt/veer-el2/.cache/"
DEBIAN_FRONTEND: "noninteractive"

steps:
- name: Install prerequisities
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git build-essential ccache libboost-all-dev
- name: Create Cache Timestamp
id: cache_timestamp
uses: nanzm/[email protected]
with:
format: 'YYYY-MM-DD-HH-mm-ss'

- name: Setup cache
uses: actions/cache@v2
timeout-minutes: 3
continue-on-error: true
with:
path: "/opt/veer-el2/.cache/"
key: cache_veer-iss_${{ steps.cache_timestamp.outputs.time }}
restore-keys: cache_veer-iss_

- name: Build VeeR-ISS
run: |
git clone https://github.com/chipsalliance/VeeR-ISS veer-iss
export CC="ccache gcc"
export CXX="ccache g++"
pushd veer-iss
git checkout 666c94e
make -j`nproc`
mkdir -p /opt/veer-iss
cp build-Linux/whisper /opt/veer-iss/
popd
cd /opt && tar -czvf veer-iss.tar.gz veer-iss/
- name: Store VeeR-ISS binaries
uses: actions/upload-artifact@v3
with:
name: veer-iss
path: /opt/*.tar.gz
retention-days: 1

tests:
name: Run RISC-V DV tests
runs-on: ubuntu-latest
needs: [verilator, spike, veer-iss]
strategy:
fail-fast: false
matrix:
test:
- riscv_arithmetic_basic_test
iss:
- spike
- whisper
env:
DEBIAN_FRONTEND: "noninteractive"

steps:
- name: Install utils
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git cpanminus ccache device-tree-compiler python3-minimal python3-pip \
libboost-all-dev gcc-riscv64-unknown-elf
sudo cpanm Bit::Vector
- name: Download Verilator binaries
uses: actions/download-artifact@v3
with:
name: verilator
path: /opt

- name: Download Spike binaries
uses: actions/download-artifact@v3
with:
name: spike
path: /opt

- name: Download VeeR-ISS binaries
uses: actions/download-artifact@v3
with:
name: veer-iss
path: /opt

- name: Unpack binaries
run: |
pushd /opt
tar -zxvf verilator.tar.gz
tar -zxvf spike.tar.gz
tar -zxvf veer-iss.tar.gz
popd
- name: Setup repository
uses: actions/checkout@v2
with:
submodules: recursive
path: veer

- name: Install Python deps
run: |
pip install -r veer/third_party/riscv-dv/requirements.txt
- name: Create Cache Timestamp
id: cache_timestamp
uses: nanzm/[email protected]
with:
format: 'YYYY-MM-DD-HH-mm-ss'

- name: Setup cache
uses: actions/cache@v2
timeout-minutes: 3
continue-on-error: true
with:
path: "/opt/veer-el2/.cache/"
key: cache_tests_${{ steps.cache_timestamp.outputs.time }}
restore-keys: cache_tests_

- name: Run test
run: |
export PATH=/opt/verilator/bin:$PATH
export PATH=/opt/veer-iss:$PATH
export RV_ROOT=`realpath veer`
export RISCV_GCC=riscv64-unknown-elf-gcc
export RISCV_OBJCOPY=riscv64-unknown-elf-objcopy
export SPIKE_PATH=/opt/spike/bin
export WHISPER_ISS=/opt/veer-iss/whisper
${RISCV_GCC} --version
pushd ${RV_ROOT}
cd tools/riscv-dv && make -j`nproc` RISCV_DV_TEST=${{ matrix.test }} RISCV_DV_ISS=${{ matrix.iss }} RISCV_DV_ITER=3 run
popd
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v3
with:
name: artifacts-${{ matrix.test }}
path: veer/tools/riscv-dv/work/test_*
3 changes: 3 additions & 0 deletions .gitmodules
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@@ -1,3 +1,6 @@
[submodule "third-party/picolibc"]
path = third_party/picolibc
url = https://github.com/picolibc/picolibc
[submodule "third_party/riscv-dv"]
path = third_party/riscv-dv
url = https://github.com/antmicro/riscv-dv
24 changes: 16 additions & 8 deletions testbench/tb_top.sv
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Expand Up @@ -105,6 +105,10 @@ module tb_top ( input bit core_clk );
logic [4:0] wb_dest;
logic [31:0] wb_data;

logic wb_csr_valid;
logic [11:0] wb_csr_dest;
logic [31:0] wb_csr_data;

`ifdef RV_BUILD_AXI4
//-------------------------- LSU AXI signals--------------------------
// AXI Write Channels
Expand Down Expand Up @@ -350,28 +354,32 @@ module tb_top ( input bit core_clk );

// trace monitor
always @(posedge core_clk) begin
wb_valid <= `DEC.dec_i0_wen_r;
wb_dest <= `DEC.dec_i0_waddr_r;
wb_data <= `DEC.dec_i0_wdata_r;
wb_valid <= `DEC.dec_i0_wen_r;
wb_dest <= `DEC.dec_i0_waddr_r;
wb_data <= `DEC.dec_i0_wdata_r;
wb_csr_valid <= `DEC.dec_csr_wen_r;
wb_csr_dest <= `DEC.dec_csr_wraddr_r;
wb_csr_data <= `DEC.dec_csr_wrdata_r;
if (trace_rv_i_valid_ip) begin
$fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", trace_rv_i_valid_ip, 0, trace_rv_i_address_ip,
0, trace_rv_i_insn_ip,trace_rv_i_exception_ip,trace_rv_i_ecause_ip,
trace_rv_i_tval_ip,trace_rv_i_interrupt_ip);
// Basic trace - no exception register updates
// #1 0 ee000000 b0201073 c 0b02 00000000
commit_count++;
$fwrite (el, "%10d : %8s 0 %h %h%13s ; %s\n", cycleCnt, $sformatf("#%0d",commit_count),
$fwrite (el, "%10d : %8s 0 %h %h%13s %14s ; %s\n", cycleCnt, $sformatf("#%0d",commit_count),
trace_rv_i_address_ip, trace_rv_i_insn_ip,
(wb_dest !=0 && wb_valid)? $sformatf("%s=%h", abi_reg[wb_dest], wb_data) : " ",
(wb_dest !=0 && wb_valid)? $sformatf("%s=%h", abi_reg[wb_dest], wb_data) : " ",
(wb_csr_valid)? $sformatf("c%h=%h", wb_csr_dest, wb_csr_data) : " ",
dasm(trace_rv_i_insn_ip, trace_rv_i_address_ip, wb_dest & {5{wb_valid}}, wb_data)
);
end
if(`DEC.dec_nonblock_load_wen) begin
$fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
$fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
tb_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
end
if(`DEC.exu_div_wren) begin
$fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);
$fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);
tb_top.gpr[0][`DEC.div_waddr_wb] = `DEC.exu_div_result;
end
end
Expand Down Expand Up @@ -422,7 +430,7 @@ module tb_top ( input bit core_clk );
$readmemh("program.hex", imem.mem);
tp = $fopen("trace_port.csv","w");
el = $fopen("exec.log","w");
$fwrite (el, "// Cycle : #inst 0 pc opcode reg=value ; mnemonic\n");
$fwrite (el, "// Cycle : #inst 0 pc opcode reg=value csr=value ; mnemonic\n");
fd = $fopen("console.log","w");
commit_count = 0;
preload_dccm();
Expand Down
1 change: 1 addition & 0 deletions third_party/riscv-dv
Submodule riscv-dv added at d30ac5
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