Added a possibility of providing user module for signal synchronization

Signed-off-by: Maciej Kurc <[email protected]>

configs/veer.config

@@ -1113,8 +1113,10 @@ our %config = (#{{{
     "even_odd_trigger_chains" => "true",                                # Whisper only
 
     "tech_specific_ec_rv_icg" => '0',
+    "tech_specific_rv_sync" => '0',
 
     "user_ec_rv_icg" => 'user_clock_gate',
+    "user_rv_sync" => 'user_rv_sync',
 );
 
 

design/dbg/el2_dbg.sv

@@ -274,7 +274,19 @@ import el2_pkg::*;
    assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode;
 
    // synchronize the rst
+`ifdef TECH_SPECIFIC_RV_SYNC
+   `USER_RV_SYNC #(
+      .WIDTH  (1),
+      .DEFAULT(1'b0)
+   ) rstl_sync (
+      .clk    (free_clk),
+      .rst_n  (dbg_rst_l),
+      .d      (rst_l),
+      .q      (rst_l_sync)
+   );
+`else
    rvsyncss #(1) rstl_syncff (.din(rst_l), .dout(rst_l_sync), .clk(free_clk), .rst_l(dbg_rst_l));
+`endif
 
    // system bus register
    // sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal

design/dmi/dmi_jtag_to_core_sync.v

@@ -44,21 +44,52 @@ reg [2:0]   rden, wren;
 assign reg_en    = c_wr_en | c_rd_en;
 assign reg_wr_en = c_wr_en;
 
+// synchronizers
+wire rden_s;
+wire wren_s;
+
+`ifdef TECH_SPECIFIC_RV_SYNC
+    `USER_RV_SYNC #(
+        .WIDTH  (2),
+        .DEFAULT(2'd0)
+     ) sync (
+        .clk    (clk),
+        .rst_n  (rst_n),
+        .d      ({rd_en, wr_en}),
+        .q      ({rden_s, wren_s})
+    );
+`else
+    reg [1:0] rden_r;
+    reg [1:0] wren_r;
+    always @ ( posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            rden_r <= '0;
+            wren_r <= '0;
+        end
+        else begin
+            rden_r <= {rden_r[0], rd_en};
+            wren_r <= {wren_r[0], wr_en};
+        end
+    end
+    assign rden_s = rden_r[1];
+    assign wren_s = wren_r[1];
+`endif
+
+// edge detectors
+reg prv_rden;
+reg prv_wren;
 
-// synchronizers  
 always @ ( posedge clk or negedge rst_n) begin
     if(!rst_n) begin
-        rden <= '0;
-        wren <= '0;
-    end
-    else begin
-        rden <= {rden[1:0], rd_en};
-        wren <= {wren[1:0], wr_en};
+        prv_rden <= 1'b0;
+        prv_wren <= 1'b0;
+    end else begin
+        prv_rden <= rden_s;
+        prv_wren <= wren_s;
     end
 end
 
-assign c_rd_en = rden[1] & ~rden[2];
-assign c_wr_en = wren[1] & ~wren[2];
-
+assign c_rd_en = prv_rden & ~rden_s;
+assign c_wr_en = prv_wren & ~wren_s;
 
 endmodule

testbench/user_cells.sv

@@ -33,3 +33,34 @@ module user_clock_gate (
     assign Q = CK & gate;
 
 endmodule
+
+// Signal synchronizing module example
+module user_rv_sync (clk, rst_n, d, q);
+
+    parameter             WIDTH     = 1;
+    parameter [WIDTH-1:0] DEFAULT   = 0;
+
+    input  logic clk;
+    input  logic rst_n;
+
+    input  logic [WIDTH-1:0] d;
+    output logic [WIDTH-1:0] q;
+
+    logic [WIDTH-1:0] r;
+
+    initial begin
+        r = DEFAULT;
+        q = DEFAULT;
+    end
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            r <= DEFAULT;
+            q <= DEFAULT;
+        end else begin
+            r <= d;
+            q <= r;
+        end
+    end
+
+endmodule