Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Adding Wolf Pack to VeeRwolves branch #75

Merged
merged 9 commits into from
Aug 24, 2024

Conversation

gsinside
Copy link
Contributor

VeeRwolves is a pack of VeeRwolf cores in a daisy-chain configuration primarily intended for comparing the capacity of FPGAs. The cores self contained and run out of ROM with GPIO and UART peripherals. The UART and GPIO outputs from each core are passed to the next in a daisy-chain fashion. The ROM code reads the UART and GPIO inputs, increments the value, and repeats the incremented value on its output so that the final output is the input value plus the number of cores.

@olofk olofk merged commit 18714ca into chipsalliance:veerwolves Aug 24, 2024
1 check passed
@olofk
Copy link
Collaborator

olofk commented Aug 24, 2024

Very good! Looks perfectly nice and clean. Thank you for your contributions. Picked and pushed

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants