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Add Axi bus behind the DMA engine #1878

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Add Axi bus behind the DMA engine #1878

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ArthurHeymans
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This rewrites the DMA engine to operate on the Axi bus which is a 64bit bus.
The recovery register interface is placed on that bus.
An Axi address offset is placed in soc_ifc.

I3C needs to be handled differently as it's on a separate bus.
adamsbridge is now integrated inside the main RTL.

It looks like uart was dropped too.

Signed-off-by: Arthur Heymans <[email protected]>
There was confusion on how that the dma engine operated on a axi bus
that replaced the apb bus. This is not true. AXI is a completely
separate bus and the DMA widget is a bridge to it.

Signed-off-by: Arthur Heymans <[email protected]>
DMA operates on a separate bus and not the root bus so remove it.

Signed-off-by: Arthur Heymans <[email protected]>
Copy most parts of the regular root bus.
Changes:
- Different type for address and data
- No poll_fn, reset_fn

Signed-off-by: Arthur Heymans <[email protected]>
Signed-off-by: Arthur Heymans <[email protected]>
This also adds the offset in the soc_ifc registers.

Signed-off-by: Arthur Heymans <[email protected]>

/// Represents an abstract AXI memory bus. Used to read and write from RAM and
/// peripheral addresses.
pub trait AxiBus {
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I absolutely hate this copy-paste. Why didn't we just increase the address size to 64-bit everywhere?

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@korran korran Jan 6, 2025

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(assuming the only reason for this change is the increased word size): my preference:

  1. Use 64-bit addresses and data in Bus trait everywhere; the 32-bit parts could ignore the high bits and error when size is 64-bit.
  2. If that's not workable for some reason we could add associated types to the existing bus trait:
trait Bus {
  type Addr: num_traits::PrimInt + num_traits::Unsigned + From<u32>;
  type Data: num_traits::PrimInt + num_traits::Unsigned + From<u32>;

  fn read(&mut self, addr: Self::Addr) -> Result<Self::Data, ()>;
  // ...
}

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poll and reset() could be moved to their own separate trait if necessary.

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3 participants