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wendallkaters committed Jan 9, 2025
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2 changes: 1 addition & 1 deletion about/index.html
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Expand Up @@ -249,7 +249,7 @@ <h2 class=blog-section-title>Recent News</h2>
<a href=https://chipsalliance.org/categories/blog>Blog</a>
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<div class=blog-post-date>
December 20, 2024
January 9, 2025
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<div class=blog-post-title>
<a href=/news/caliptra-support-for-veer/>Caliptra - Support for VeeR EL2 with User Mode and Physical Memory Protection in Tock embedded OS</a>
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Expand Up @@ -122,7 +122,7 @@ <h1 class=blog-hero-title>Blog</h1>
<a href=https://chipsalliance.org/categories/blog>Blog</a>
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<div class=blog-post-date>
December 20, 2024
January 9, 2025
</div>
<div class=blog-post-title>
<a href=/news/caliptra-support-for-veer/>Caliptra - Support for VeeR EL2 with User Mode and Physical Memory Protection in Tock embedded OS</a>
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2 changes: 1 addition & 1 deletion categories/blog/index.xml
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<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Blog on CHIPS Alliance</title><link>https://chipsalliance.org/categories/blog/</link><description>Recent content in Blog on CHIPS Alliance</description><generator>Hugo -- gohugo.io</generator><language>en-us</language><lastBuildDate>Fri, 20 Dec 2024 00:00:00 +0000</lastBuildDate><atom:link href="https://chipsalliance.org/categories/blog/index.xml" rel="self" type="application/rss+xml"/><item><title>Caliptra - Support for VeeR EL2 with User Mode and Physical Memory Protection in Tock embedded OS</title><link>https://chipsalliance.org/news/caliptra-support-for-veer/</link><pubDate>Fri, 20 Dec 2024 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/news/caliptra-support-for-veer/</guid><description>The Caliptra Root of Trust project, a collaboration between AMD, Google, Microsoft and NVIDIA within the CHIPS Alliance, is steadily heading towards its 2.0 release – an effort Antmicro is actively contributing to. They’ve recently described their implementation of User mode in the RISC-V VeeR EL2 core along with extended Physical Memory Protection, and related to this work, they’ve introduced support for VeeR EL2 with User Mode and PMP to the Tock embedded OS.</description></item><item><title>Topwrap – open source toolkit for modular, parameterizable digital logic design</title><link>https://chipsalliance.org/news/topwrap/</link><pubDate>Fri, 20 Dec 2024 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/news/topwrap/</guid><description>ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. Taking advantage of this modularity and enabling automation and reuse of blocks across designs requires tools for automated processing and generation of top level files, letting you easily parametrize and aggregate the blocks in various configurations.
<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Blog on CHIPS Alliance</title><link>https://chipsalliance.org/categories/blog/</link><description>Recent content in Blog on CHIPS Alliance</description><generator>Hugo -- gohugo.io</generator><language>en-us</language><lastBuildDate>Thu, 09 Jan 2025 00:00:00 +0000</lastBuildDate><atom:link href="https://chipsalliance.org/categories/blog/index.xml" rel="self" type="application/rss+xml"/><item><title>Caliptra - Support for VeeR EL2 with User Mode and Physical Memory Protection in Tock embedded OS</title><link>https://chipsalliance.org/news/caliptra-support-for-veer/</link><pubDate>Thu, 09 Jan 2025 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/news/caliptra-support-for-veer/</guid><description>The Caliptra Root of Trust project, a collaboration between AMD, Google, Microsoft and NVIDIA within the CHIPS Alliance, is steadily heading towards its 2.0 release – an effort Antmicro is actively contributing to. They’ve recently described their implementation of User mode in the RISC-V VeeR EL2 core along with extended Physical Memory Protection, and related to this work, they’ve introduced support for VeeR EL2 with User Mode and PMP to the Tock embedded OS.</description></item><item><title>Topwrap – open source toolkit for modular, parameterizable digital logic design</title><link>https://chipsalliance.org/news/topwrap/</link><pubDate>Fri, 20 Dec 2024 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/news/topwrap/</guid><description>ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. Taking advantage of this modularity and enabling automation and reuse of blocks across designs requires tools for automated processing and generation of top level files, letting you easily parametrize and aggregate the blocks in various configurations.
To this end, Antmicro created Topwrap, an open source toolkit for connecting individual HDL modules into full designs of varying complexity.</description></item><item><title>Caliptra @ OCP Global Summit 2024</title><link>https://chipsalliance.org/news/caliptra-ocp-global-summit-2024/</link><pubDate>Sun, 13 Oct 2024 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/news/caliptra-ocp-global-summit-2024/</guid><description>Introduction As we continue to advance the field of hardware security, we are thrilled to celebrate the successful integration of Caliptra 1.x by our esteemed partners. Their commitment to enhancing security through the adoption of our open-source Root of Trust (RoT) is a testament to the collaborative spirit of the Open Compute Project (OCP). In this post, we also look ahead to the exciting developments planned for Caliptra 2.0.
Recognizing Caliptra 1.</description></item><item><title>Initial assertion control support in Verilator</title><link>https://chipsalliance.org/news/initial-assertion-control-support-in-verilator/</link><pubDate>Fri, 21 Jun 2024 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/news/initial-assertion-control-support-in-verilator/</guid><description>Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&amp;amp;D projects. Extending Verilator with new verification features is a prominent example of such efforts, with the latest notable improvements including initial support for UVM testbenches, the astsee tool for Verilator process and AST analysis and constrained randomization.
In this article, Antmicro introduces initial support for global assertion control (already part of mainline Verilator), building on existing support for assertions available in the simulator.</description></item><item><title>Speeding Up OpenROAD For Fast Design Feedback</title><link>https://chipsalliance.org/news/speeding-up-openroad-for-fast-design-feedback/</link><pubDate>Fri, 24 May 2024 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/news/speeding-up-openroad-for-fast-design-feedback/</guid><description>The OpenROAD project provides an open source ASIC toolchain that reduces the entry barriers to the field of hardware development and allows fast-turnaround feedback about designs, helping to increase the productivity of silicon teams. As such, it’s a great supporting tool, increasingly used in state-of-the-art industrial projects alongside other open source tools like Verilator.
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Expand Up @@ -119,7 +119,7 @@ <h1 class=blog-hero-title>Categories</h1>
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December 20, 2024
January 9, 2025
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<a href=/categories/blog/>Blog</a>
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<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Categories on CHIPS Alliance</title><link>https://chipsalliance.org/categories/</link><description>Recent content in Categories on CHIPS Alliance</description><generator>Hugo -- gohugo.io</generator><language>en-us</language><lastBuildDate>Fri, 20 Dec 2024 00:00:00 +0000</lastBuildDate><atom:link href="https://chipsalliance.org/categories/index.xml" rel="self" type="application/rss+xml"/><item><title>Blog</title><link>https://chipsalliance.org/categories/blog/</link><pubDate>Fri, 20 Dec 2024 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/categories/blog/</guid><description/></item><item><title>Announcements</title><link>https://chipsalliance.org/categories/announcements/</link><pubDate>Tue, 13 Dec 2022 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/categories/announcements/</guid><description/></item><item><title>Reports</title><link>https://chipsalliance.org/categories/reports/</link><pubDate>Sat, 01 Jan 2022 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/categories/reports/</guid><description/></item></channel></rss>
<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Categories on CHIPS Alliance</title><link>https://chipsalliance.org/categories/</link><description>Recent content in Categories on CHIPS Alliance</description><generator>Hugo -- gohugo.io</generator><language>en-us</language><lastBuildDate>Thu, 09 Jan 2025 00:00:00 +0000</lastBuildDate><atom:link href="https://chipsalliance.org/categories/index.xml" rel="self" type="application/rss+xml"/><item><title>Blog</title><link>https://chipsalliance.org/categories/blog/</link><pubDate>Thu, 09 Jan 2025 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/categories/blog/</guid><description/></item><item><title>Announcements</title><link>https://chipsalliance.org/categories/announcements/</link><pubDate>Tue, 13 Dec 2022 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/categories/announcements/</guid><description/></item><item><title>Reports</title><link>https://chipsalliance.org/categories/reports/</link><pubDate>Sat, 01 Jan 2022 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/categories/reports/</guid><description/></item></channel></rss>
2 changes: 1 addition & 1 deletion index.html
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Expand Up @@ -424,7 +424,7 @@ <h2 class=blog-section-title>Recent News</h2>
<a href=https://chipsalliance.org/categories/blog>Blog</a>
</div>
<div class=blog-post-date>
December 20, 2024
January 9, 2025
</div>
<div class=blog-post-title>
<a href=/news/caliptra-support-for-veer/>Caliptra - Support for VeeR EL2 with User Mode and Physical Memory Protection in Tock embedded OS</a>
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