[ci] output urg report in vcs flow

chipsalliance · Oct 6, 2024 · 91f1478 · 91f1478
1 parent e87063a
commit 91f1478
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Showing 2 changed files with 5 additions and 2 deletions.
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -56,7 +56,7 @@ jobs:
           ref: ${{ github.event.pull_request.head.sha }}
       - name: "Run VCS"
         run: |
-          nix build '.#gcd.vcs.tests.simple-sim' --impure -L
+          nix build '.#gcd.vcs.tests.simple-sim' --impure -L && cat result/urgReport/asserts.txt
 
   run-verilator:
     name: "Run Verilator"

diff --git a/templates/chisel/nix/gcd/vcs.nix b/templates/chisel/nix/gcd/vcs.nix
@@ -48,7 +48,7 @@ stdenv.mkDerivation (finalAttr: {
       } \
       ${
         lib.optionalString enableCover ''
-          -cm line+cond+fsm+tgl+branch+assert \
+          -cm assert \
           -cm_dir ${coverageName} ''
       } \
       -file filelist.f \
@@ -69,8 +69,11 @@ stdenv.mkDerivation (finalAttr: {
       export DATA_ONLY=1
       ${finalAttr.finalPackage}/bin/${binName}
 
+      ${vcs-fhs-env}/bin/vcs-fhs-env -c "urg -dir "$GCD_SIM_RESULT_DIR"/result/${coverageName} -format text"
+
       mkdir -p "$out"
       cp -vr "$GCD_SIM_RESULT_DIR"/result/* "$out/"
+      cp -vr ./urgReport "$out/"
     '';
   };