Skip to content
run-tests

Merge pull request #956 from antmicro/ci-matrix #111

Sign in to view logs

Merge pull request #956 from antmicro/ci-matrix

Merge pull request #956 from antmicro/ci-matrix #111

Run time

Learn about OS pricing on GitHub Actions
Job Run time
generate-config
5s
build-spike / Build Spike
7m 44s
generate-code (riscv_arithmetic_basic_test, uvm)
3m 9s
generate-code (riscv_rand_instr_test, uvm)
3m 5s
generate-code (riscv_jump_stress_test, uvm)
3m 0s
generate-code (riscv_loop_test, uvm)
3m 9s
generate-code (riscv_rand_jump_test, uvm)
3m 0s
generate-code (riscv_mmu_stress_test, uvm)
3m 25s
generate-code (riscv_no_fence_test, uvm)
3m 8s
generate-code (riscv_illegal_instr_test, uvm)
3m 7s
generate-code (riscv_ebreak_test, uvm)
3m 22s
generate-code (riscv_ebreak_debug_mode_test, uvm)
6m 29s
generate-code (riscv_full_interrupt_test, uvm)
3m 9s
generate-code (riscv_unaligned_load_store_test, uvm)
3m 10s
generate-code (riscv_non_compressed_instr_test, uvm)
3m 11s
generate-code (riscv_hint_instr_test, uvm)
3m 29s
generate-code (riscv_pmp_test, uvm)
3m 4s
generate-code (riscv_arithmetic_basic_test, pyflow)
4m 7s
run-tests (riscv_arithmetic_basic_test, uvm)
43s
run-tests (riscv_rand_instr_test, uvm)
45s
run-tests (riscv_jump_stress_test, uvm)
37s
run-tests (riscv_loop_test, uvm)
45s
run-tests (riscv_rand_jump_test, uvm)
41s
run-tests (riscv_mmu_stress_test, uvm)
46s
run-tests (riscv_no_fence_test, uvm)
45s
run-tests (riscv_illegal_instr_test, uvm)
38s
run-tests (riscv_ebreak_test, uvm)
47s
run-tests (riscv_ebreak_debug_mode_test, uvm)
37s
run-tests (riscv_full_interrupt_test, uvm)
45s
run-tests (riscv_unaligned_load_store_test, uvm)
50s
run-tests (riscv_non_compressed_instr_test, uvm)
49s
run-tests (riscv_hint_instr_test, uvm)
37s
run-tests (riscv_pmp_test, uvm)
45s
run-tests (riscv_arithmetic_basic_test, pyflow)
40s
1h 14m 23s