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allow specifying privilege modes for simulation #103

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allow specifying privilege modes for simulation

allow specifying privilege modes for simulation #103

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Job Run time
generate-config
6s
generate-config
6s
generate-config
6s
generate-config
6s
build-spike / Build Spike
7m 46s
build-spike / Build Spike
7m 46s
build-spike / Build Spike
7m 46s
build-spike / Build Spike
8m 8s
generate-code (riscv_arithmetic_basic_test, uvm)
20m 15s
generate-code (riscv_arithmetic_basic_test, uvm)
19m 39s
generate-code (riscv_arithmetic_basic_test, uvm)
19m 26s
generate-code (riscv_arithmetic_basic_test, uvm)
1s
generate-code (riscv_rand_instr_test, uvm)
20m 10s
generate-code (riscv_rand_instr_test, uvm)
20m 50s
generate-code (riscv_rand_instr_test, uvm)
19m 18s
generate-code (riscv_rand_instr_test, uvm)
1s
generate-code (riscv_jump_stress_test, uvm)
19m 48s
generate-code (riscv_jump_stress_test, uvm)
19m 53s
generate-code (riscv_jump_stress_test, uvm)
19m 21s
generate-code (riscv_jump_stress_test, uvm)
1s
generate-code (riscv_loop_test, uvm)
19m 31s
generate-code (riscv_loop_test, uvm)
19m 51s
generate-code (riscv_loop_test, uvm)
19m 55s
generate-code (riscv_loop_test, uvm)
1s
generate-code (riscv_rand_jump_test, uvm)
19m 31s
generate-code (riscv_rand_jump_test, uvm)
19m 43s
generate-code (riscv_rand_jump_test, uvm)
20m 23s
generate-code (riscv_rand_jump_test, uvm)
1s
generate-code (riscv_mmu_stress_test, uvm)
19m 43s
generate-code (riscv_mmu_stress_test, uvm)
19m 51s
generate-code (riscv_mmu_stress_test, uvm)
20m 24s
generate-code (riscv_mmu_stress_test, uvm)
1s
generate-code (riscv_no_fence_test, uvm)
19m 33s
generate-code (riscv_no_fence_test, uvm)
20m 50s
generate-code (riscv_no_fence_test, uvm)
19m 22s
generate-code (riscv_no_fence_test, uvm)
1s
generate-code (riscv_illegal_instr_test, uvm)
19m 46s
generate-code (riscv_illegal_instr_test, uvm)
20m 47s
generate-code (riscv_illegal_instr_test, uvm)
20m 14s
generate-code (riscv_illegal_instr_test, uvm)
1s
generate-code (riscv_ebreak_test, uvm)
19m 49s
generate-code (riscv_ebreak_test, uvm)
19m 51s
generate-code (riscv_ebreak_test, uvm)
19m 51s
generate-code (riscv_ebreak_test, uvm)
1s
generate-code (riscv_ebreak_debug_mode_test, uvm)
19m 29s
generate-code (riscv_ebreak_debug_mode_test, uvm)
19m 34s
generate-code (riscv_ebreak_debug_mode_test, uvm)
19m 57s
generate-code (riscv_ebreak_debug_mode_test, uvm)
1s
generate-code (riscv_full_interrupt_test, uvm)
20m 4s
generate-code (riscv_full_interrupt_test, uvm)
19m 37s
generate-code (riscv_full_interrupt_test, uvm)
19m 21s
generate-code (riscv_full_interrupt_test, uvm)
1s
generate-code (riscv_unaligned_load_store_test, uvm)
19m 27s
generate-code (riscv_unaligned_load_store_test, uvm)
20m 48s
generate-code (riscv_unaligned_load_store_test, uvm)
19m 21s
generate-code (riscv_unaligned_load_store_test, uvm)
1s
generate-code (riscv_non_compressed_instr_test, uvm)
19m 51s
generate-code (riscv_non_compressed_instr_test, uvm)
19m 46s
generate-code (riscv_non_compressed_instr_test, uvm)
19m 22s
generate-code (riscv_non_compressed_instr_test, uvm)
1s
generate-code (riscv_hint_instr_test, uvm)
20m 10s
generate-code (riscv_hint_instr_test, uvm)
20m 51s
generate-code (riscv_hint_instr_test, uvm)
19m 23s
generate-code (riscv_hint_instr_test, uvm)
1s
generate-code (riscv_pmp_test, uvm)
19m 43s
generate-code (riscv_pmp_test, uvm)
19m 42s
generate-code (riscv_pmp_test, uvm)
19m 43s
generate-code (riscv_pmp_test, uvm)
1s
generate-code (riscv_arithmetic_basic_test, pyflow)
3m 58s
generate-code (riscv_arithmetic_basic_test, pyflow)
3m 58s
generate-code (riscv_arithmetic_basic_test, pyflow)
3m 58s
generate-code (riscv_arithmetic_basic_test, pyflow)
1s
run-tests
0s
run-tests
0s
run-tests
0s
run-tests
0s
15h 37m 44s