run: fix disabling the `c` extension #108

Run time

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Job	Run time
generate-config	7s
generate-config	7s
generate-config	7s
generate-config	6s
generate-config	6s
generate-config	6s
generate-config	6s
generate-config	6s
generate-config	6s
generate-config	6s
generate-config	6s
generate-config	6s
generate-config	9s
generate-config	9s
generate-config	9s
generate-config	4s
build-spike / Build Spike	6s
build-spike / Build Spike	6s
build-spike / Build Spike	6s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	7m 37s
build-spike / Build Spike	3m 13s
build-spike / Build Spike	3m 13s
build-spike / Build Spike	3m 13s
build-spike / Build Spike	3m 3s
generate-code (riscv_arithmetic_basic_test, uvm)	1h 2m 53s
generate-code (riscv_arithmetic_basic_test, uvm)	1s
generate-code (riscv_arithmetic_basic_test, uvm)	1s
generate-code (riscv_arithmetic_basic_test, uvm)	1s
generate-code (riscv_arithmetic_basic_test, uvm)	1s
generate-code (riscv_arithmetic_basic_test, uvm)	1s
generate-code (riscv_arithmetic_basic_test, uvm)	1s
generate-code (riscv_arithmetic_basic_test, uvm)	1s
generate-code (riscv_arithmetic_basic_test, uvm)	1h 3m 6s
generate-code (riscv_arithmetic_basic_test, uvm)	1h 6m 45s
generate-code (riscv_arithmetic_basic_test, uvm)	1h 2m 56s
generate-code (riscv_arithmetic_basic_test, uvm)	1h 3m 4s
generate-code (riscv_arithmetic_basic_test, uvm)	1m 34s
generate-code (riscv_arithmetic_basic_test, uvm)	1m 40s
generate-code (riscv_arithmetic_basic_test, uvm)	1m 29s
generate-code (riscv_arithmetic_basic_test, uvm)	1m 30s
generate-code (riscv_rand_instr_test, uvm)	1h 2m 59s
generate-code (riscv_rand_instr_test, uvm)	1h 2m 59s
generate-code (riscv_rand_instr_test, uvm)	1s
generate-code (riscv_rand_instr_test, uvm)	1s
generate-code (riscv_rand_instr_test, uvm)	1s
generate-code (riscv_rand_instr_test, uvm)	1s
generate-code (riscv_rand_instr_test, uvm)	1s
generate-code (riscv_rand_instr_test, uvm)	1s
generate-code (riscv_rand_instr_test, uvm)	1h 3m 8s
generate-code (riscv_rand_instr_test, uvm)	1h 3m 8s
generate-code (riscv_rand_instr_test, uvm)	1h 3m 8s
generate-code (riscv_rand_instr_test, uvm)	1h 3m 8s
generate-code (riscv_rand_instr_test, uvm)	1m 37s
generate-code (riscv_rand_instr_test, uvm)	1m 37s
generate-code (riscv_rand_instr_test, uvm)	1m 37s
generate-code (riscv_rand_instr_test, uvm)	1h 2m 51s
generate-code (riscv_jump_stress_test, uvm)	1h 2m 56s
generate-code (riscv_jump_stress_test, uvm)	1h 2m 56s
generate-code (riscv_jump_stress_test, uvm)	1s
generate-code (riscv_jump_stress_test, uvm)	1s
generate-code (riscv_jump_stress_test, uvm)	1s
generate-code (riscv_jump_stress_test, uvm)	1s
generate-code (riscv_jump_stress_test, uvm)	1s
generate-code (riscv_jump_stress_test, uvm)	1s
generate-code (riscv_jump_stress_test, uvm)	1h 3m 27s
generate-code (riscv_jump_stress_test, uvm)	1h 3m 27s
generate-code (riscv_jump_stress_test, uvm)	1h 3m 27s
generate-code (riscv_jump_stress_test, uvm)	1h 3m 27s
generate-code (riscv_jump_stress_test, uvm)	1m 34s
generate-code (riscv_jump_stress_test, uvm)	1m 34s
generate-code (riscv_jump_stress_test, uvm)	1m 34s
generate-code (riscv_jump_stress_test, uvm)	1h 3m 8s
generate-code (riscv_loop_test, uvm)	1h 2m 54s
generate-code (riscv_loop_test, uvm)	1h 2m 54s
generate-code (riscv_loop_test, uvm)	1s
generate-code (riscv_loop_test, uvm)	1s
generate-code (riscv_loop_test, uvm)	1s
generate-code (riscv_loop_test, uvm)	1s
generate-code (riscv_loop_test, uvm)	1s
generate-code (riscv_loop_test, uvm)	1s
generate-code (riscv_loop_test, uvm)	1h 3m 34s
generate-code (riscv_loop_test, uvm)	1h 3m 34s
generate-code (riscv_loop_test, uvm)	1h 3m 34s
generate-code (riscv_loop_test, uvm)	1h 3m 34s
generate-code (riscv_loop_test, uvm)	1m 35s
generate-code (riscv_loop_test, uvm)	1m 35s
generate-code (riscv_loop_test, uvm)	1m 35s
generate-code (riscv_loop_test, uvm)	1h 2m 58s
generate-code (riscv_rand_jump_test, uvm)	1h 3m 6s
generate-code (riscv_rand_jump_test, uvm)	1h 3m 6s
generate-code (riscv_rand_jump_test, uvm)	1s
generate-code (riscv_rand_jump_test, uvm)	1s
generate-code (riscv_rand_jump_test, uvm)	1s
generate-code (riscv_rand_jump_test, uvm)	1s
generate-code (riscv_rand_jump_test, uvm)	1s
generate-code (riscv_rand_jump_test, uvm)	1s
generate-code (riscv_rand_jump_test, uvm)	1h 3m 25s
generate-code (riscv_rand_jump_test, uvm)	1h 3m 25s
generate-code (riscv_rand_jump_test, uvm)	1h 3m 25s
generate-code (riscv_rand_jump_test, uvm)	1h 3m 25s
generate-code (riscv_rand_jump_test, uvm)	1m 31s
generate-code (riscv_rand_jump_test, uvm)	1m 31s
generate-code (riscv_rand_jump_test, uvm)	1m 31s
generate-code (riscv_rand_jump_test, uvm)	1h 3m 18s
generate-code (riscv_mmu_stress_test, uvm)	1h 3m 0s
generate-code (riscv_mmu_stress_test, uvm)	1h 3m 0s
generate-code (riscv_mmu_stress_test, uvm)	1s
generate-code (riscv_mmu_stress_test, uvm)	1s
generate-code (riscv_mmu_stress_test, uvm)	1s
generate-code (riscv_mmu_stress_test, uvm)	1s
generate-code (riscv_mmu_stress_test, uvm)	1s
generate-code (riscv_mmu_stress_test, uvm)	1s
generate-code (riscv_mmu_stress_test, uvm)	1h 3m 11s
generate-code (riscv_mmu_stress_test, uvm)	1h 3m 11s
generate-code (riscv_mmu_stress_test, uvm)	1h 3m 11s
generate-code (riscv_mmu_stress_test, uvm)	1h 3m 11s
generate-code (riscv_mmu_stress_test, uvm)	1m 35s
generate-code (riscv_mmu_stress_test, uvm)	1m 35s
generate-code (riscv_mmu_stress_test, uvm)	1m 35s
generate-code (riscv_mmu_stress_test, uvm)	1h 3m 9s
generate-code (riscv_no_fence_test, uvm)	1h 3m 0s
generate-code (riscv_no_fence_test, uvm)	1h 3m 0s
generate-code (riscv_no_fence_test, uvm)	1s
generate-code (riscv_no_fence_test, uvm)	1s
generate-code (riscv_no_fence_test, uvm)	1s
generate-code (riscv_no_fence_test, uvm)	1s
generate-code (riscv_no_fence_test, uvm)	1s
generate-code (riscv_no_fence_test, uvm)	1s
generate-code (riscv_no_fence_test, uvm)	1h 2m 57s
generate-code (riscv_no_fence_test, uvm)	1h 2m 57s
generate-code (riscv_no_fence_test, uvm)	1h 2m 57s
generate-code (riscv_no_fence_test, uvm)	1h 2m 57s
generate-code (riscv_no_fence_test, uvm)	1m 35s
generate-code (riscv_no_fence_test, uvm)	1m 35s
generate-code (riscv_no_fence_test, uvm)	1m 35s
generate-code (riscv_no_fence_test, uvm)	1h 3m 8s
generate-code (riscv_illegal_instr_test, uvm)	1h 2m 48s
generate-code (riscv_illegal_instr_test, uvm)	1h 2m 48s
generate-code (riscv_illegal_instr_test, uvm)	1s
generate-code (riscv_illegal_instr_test, uvm)	1s
generate-code (riscv_illegal_instr_test, uvm)	1s
generate-code (riscv_illegal_instr_test, uvm)	1s
generate-code (riscv_illegal_instr_test, uvm)	1s
generate-code (riscv_illegal_instr_test, uvm)	1s
generate-code (riscv_illegal_instr_test, uvm)	1h 2m 53s
generate-code (riscv_illegal_instr_test, uvm)	1h 2m 53s
generate-code (riscv_illegal_instr_test, uvm)	1h 2m 53s
generate-code (riscv_illegal_instr_test, uvm)	1h 2m 53s
generate-code (riscv_illegal_instr_test, uvm)	1m 34s
generate-code (riscv_illegal_instr_test, uvm)	1m 34s
generate-code (riscv_illegal_instr_test, uvm)	1m 34s
generate-code (riscv_illegal_instr_test, uvm)	1h 3m 11s
generate-code (riscv_ebreak_test, uvm)	1h 2m 46s
generate-code (riscv_ebreak_test, uvm)	1h 2m 46s
generate-code (riscv_ebreak_test, uvm)	1s
generate-code (riscv_ebreak_test, uvm)	1s
generate-code (riscv_ebreak_test, uvm)	1s
generate-code (riscv_ebreak_test, uvm)	1s
generate-code (riscv_ebreak_test, uvm)	1s
generate-code (riscv_ebreak_test, uvm)	1s
generate-code (riscv_ebreak_test, uvm)	1h 2m 48s
generate-code (riscv_ebreak_test, uvm)	1h 2m 48s
generate-code (riscv_ebreak_test, uvm)	1h 2m 48s
generate-code (riscv_ebreak_test, uvm)	1h 2m 48s
generate-code (riscv_ebreak_test, uvm)	1m 31s
generate-code (riscv_ebreak_test, uvm)	1m 31s
generate-code (riscv_ebreak_test, uvm)	1m 31s
generate-code (riscv_ebreak_test, uvm)	1h 3m 5s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1h 2m 57s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1h 2m 57s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1h 3m 33s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1h 3m 33s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1h 3m 33s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1h 3m 33s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1m 36s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1m 36s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1m 36s
generate-code (riscv_ebreak_debug_mode_test, uvm)	1h 3m 8s
generate-code (riscv_full_interrupt_test, uvm)	1h 3m 5s
generate-code (riscv_full_interrupt_test, uvm)	1h 3m 5s
generate-code (riscv_full_interrupt_test, uvm)	1s
generate-code (riscv_full_interrupt_test, uvm)	1s
generate-code (riscv_full_interrupt_test, uvm)	1s
generate-code (riscv_full_interrupt_test, uvm)	1s
generate-code (riscv_full_interrupt_test, uvm)	1s
generate-code (riscv_full_interrupt_test, uvm)	1s
generate-code (riscv_full_interrupt_test, uvm)	1h 3m 30s
generate-code (riscv_full_interrupt_test, uvm)	1h 3m 30s
generate-code (riscv_full_interrupt_test, uvm)	1h 3m 30s
generate-code (riscv_full_interrupt_test, uvm)	1h 3m 30s
generate-code (riscv_full_interrupt_test, uvm)	1m 35s
generate-code (riscv_full_interrupt_test, uvm)	1m 35s
generate-code (riscv_full_interrupt_test, uvm)	1m 35s
generate-code (riscv_full_interrupt_test, uvm)	1h 2m 53s
generate-code (riscv_unaligned_load_store_test, uvm)	1h 3m 3s
generate-code (riscv_unaligned_load_store_test, uvm)	1h 3m 3s
generate-code (riscv_unaligned_load_store_test, uvm)	1s
generate-code (riscv_unaligned_load_store_test, uvm)	1s
generate-code (riscv_unaligned_load_store_test, uvm)	1s
generate-code (riscv_unaligned_load_store_test, uvm)	1s
generate-code (riscv_unaligned_load_store_test, uvm)	1s
generate-code (riscv_unaligned_load_store_test, uvm)	1s
generate-code (riscv_unaligned_load_store_test, uvm)	1h 3m 9s
generate-code (riscv_unaligned_load_store_test, uvm)	1h 3m 9s
generate-code (riscv_unaligned_load_store_test, uvm)	1h 3m 9s
generate-code (riscv_unaligned_load_store_test, uvm)	1h 3m 9s
generate-code (riscv_unaligned_load_store_test, uvm)	1m 35s
generate-code (riscv_unaligned_load_store_test, uvm)	1m 35s
generate-code (riscv_unaligned_load_store_test, uvm)	1m 35s
generate-code (riscv_unaligned_load_store_test, uvm)	1h 3m 6s
generate-code (riscv_non_compressed_instr_test, uvm)	1h 2m 52s
generate-code (riscv_non_compressed_instr_test, uvm)	1h 2m 52s
generate-code (riscv_non_compressed_instr_test, uvm)	1s
generate-code (riscv_non_compressed_instr_test, uvm)	1s
generate-code (riscv_non_compressed_instr_test, uvm)	1s
generate-code (riscv_non_compressed_instr_test, uvm)	1s
generate-code (riscv_non_compressed_instr_test, uvm)	1s
generate-code (riscv_non_compressed_instr_test, uvm)	1s
generate-code (riscv_non_compressed_instr_test, uvm)	1h 2m 46s
generate-code (riscv_non_compressed_instr_test, uvm)	1h 2m 46s
generate-code (riscv_non_compressed_instr_test, uvm)	1h 2m 46s
generate-code (riscv_non_compressed_instr_test, uvm)	1h 2m 46s
generate-code (riscv_non_compressed_instr_test, uvm)	1m 33s
generate-code (riscv_non_compressed_instr_test, uvm)	1m 33s
generate-code (riscv_non_compressed_instr_test, uvm)	1m 33s
generate-code (riscv_non_compressed_instr_test, uvm)	1h 2m 52s
generate-code (riscv_hint_instr_test, uvm)	1h 3m 2s
generate-code (riscv_hint_instr_test, uvm)	1h 3m 2s
generate-code (riscv_hint_instr_test, uvm)	1s
generate-code (riscv_hint_instr_test, uvm)	1s
generate-code (riscv_hint_instr_test, uvm)	1s
generate-code (riscv_hint_instr_test, uvm)	1s
generate-code (riscv_hint_instr_test, uvm)	1s
generate-code (riscv_hint_instr_test, uvm)	1s
generate-code (riscv_hint_instr_test, uvm)	1h 3m 25s
generate-code (riscv_hint_instr_test, uvm)	1h 3m 25s
generate-code (riscv_hint_instr_test, uvm)	1h 3m 25s
generate-code (riscv_hint_instr_test, uvm)	1h 3m 25s
generate-code (riscv_hint_instr_test, uvm)	1m 39s
generate-code (riscv_hint_instr_test, uvm)	1m 39s
generate-code (riscv_hint_instr_test, uvm)	1m 39s
generate-code (riscv_hint_instr_test, uvm)	1h 2m 52s
generate-code (riscv_pmp_test, uvm)	1h 2m 55s
generate-code (riscv_pmp_test, uvm)	1h 2m 55s
generate-code (riscv_pmp_test, uvm)	1s
generate-code (riscv_pmp_test, uvm)	1s
generate-code (riscv_pmp_test, uvm)	1s
generate-code (riscv_pmp_test, uvm)	1s
generate-code (riscv_pmp_test, uvm)	1s
generate-code (riscv_pmp_test, uvm)	1s
generate-code (riscv_pmp_test, uvm)	1h 2m 56s
generate-code (riscv_pmp_test, uvm)	1h 2m 56s
generate-code (riscv_pmp_test, uvm)	1h 2m 56s
generate-code (riscv_pmp_test, uvm)	1h 2m 56s
generate-code (riscv_pmp_test, uvm)	1m 36s
generate-code (riscv_pmp_test, uvm)	1m 36s
generate-code (riscv_pmp_test, uvm)	1m 36s
generate-code (riscv_pmp_test, uvm)	1h 2m 48s
generate-code (riscv_arithmetic_basic_test, pyflow)	2m 2s
generate-code (riscv_arithmetic_basic_test, pyflow)	2m 2s
generate-code (riscv_arithmetic_basic_test, pyflow)	2m 2s
generate-code (riscv_arithmetic_basic_test, pyflow)	1s
generate-code (riscv_arithmetic_basic_test, pyflow)	1s
generate-code (riscv_arithmetic_basic_test, pyflow)	1s
generate-code (riscv_arithmetic_basic_test, pyflow)	1s
generate-code (riscv_arithmetic_basic_test, pyflow)	1s
generate-code (riscv_arithmetic_basic_test, pyflow)	4m 9s
generate-code (riscv_arithmetic_basic_test, pyflow)	4m 9s
generate-code (riscv_arithmetic_basic_test, pyflow)	4m 9s
generate-code (riscv_arithmetic_basic_test, pyflow)	4m 9s
generate-code (riscv_arithmetic_basic_test, pyflow)	1m 33s
generate-code (riscv_arithmetic_basic_test, pyflow)	1m 33s
generate-code (riscv_arithmetic_basic_test, pyflow)	1m 33s
generate-code (riscv_arithmetic_basic_test, pyflow)	1m 32s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests	0s
run-tests (riscv_arithmetic_basic_test, uvm)	51s
run-tests (riscv_rand_instr_test, uvm)	52s
run-tests (riscv_jump_stress_test, uvm)	38s
run-tests (riscv_loop_test, uvm)	41s
run-tests (riscv_rand_jump_test, uvm)	47s
run-tests (riscv_mmu_stress_test, uvm)	47s
run-tests (riscv_no_fence_test, uvm)	46s
run-tests (riscv_illegal_instr_test, uvm)	48s
run-tests (riscv_ebreak_test, uvm)	46s
run-tests (riscv_ebreak_debug_mode_test, uvm)	38s
run-tests (riscv_full_interrupt_test, uvm)	42s
run-tests (riscv_unaligned_load_store_test, uvm)	45s
run-tests (riscv_non_compressed_instr_test, uvm)	52s
run-tests (riscv_hint_instr_test, uvm)	39s
run-tests (riscv_pmp_test, uvm)	43s
run-tests (riscv_arithmetic_basic_test, pyflow)	54s
	4d 15h 41m 13s

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run: fix disabling the `c` extension #108

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run: fix disabling the `c` extension #108

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run: fix disabling the c extension #108

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run: fix disabling the `c` extension #108