[difftest] impl indexed read

difftest/online_drive/src/dpi.rs

@@ -19,15 +19,6 @@ pub type SvBitVecVal = u32;
 
 pub(crate) struct AxiReadPayload {
   pub(crate) data: Vec<u8>,
-  #[allow(dead_code)]
-  pub(crate) beats: u8,
-}
-
-pub(crate) struct AxiReadIndexedPayload {
-  #[allow(dead_code)]
-  pub(crate) data: [u8; 256 * 4],
-  #[allow(dead_code)]
-  pub(crate) beats: u8,
 }
 
 fn write_to_pointer(dst: *mut u8, data: &Vec<u8>, n: usize) {
@@ -43,7 +34,6 @@ unsafe fn fill_axi_read_payload(dst: *mut SvBitVecVal, dlen: u32, payload: AxiRe
   assert!(payload.data.len() <= data_len);
   let dst = dst as *mut u8;
   write_to_pointer(dst, &payload.data, payload.data.len());
-  ptr::write(dst.offset(data_len as isize), payload.beats);
 }
 
 #[repr(C, packed)]
@@ -116,11 +106,11 @@ unsafe extern "C" fn axi_read_highBandwidthPort_rs(
   arregion: c_longlong,
   payload: *mut SvBitVecVal,
 ) {
-  debug!("axi_read_highBandwidth (channel_id={channel_id}, arid={arid}, araddr={araddr}, \
+  debug!("axi_read_highBandwidth (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
   arlen={arlen}, arsize={arsize}, arburst={arburst}, arlock={arlock}, arcache={arcache}, \
   arprot={arprot}, arqos={arqos}, arregion={arregion})");
   let driver = &mut *(target as *mut Driver);
-  let response = driver.axi_read_high_bandwidth(araddr as u64, arsize as u64);
+  let response = driver.axi_read_high_bandwidth(araddr as u32, arsize as u64);
   fill_axi_read_payload(payload, driver.dlen, response);
 }
 
@@ -140,11 +130,12 @@ unsafe extern "C" fn axi_read_indexedAccessPort_rs(
   arregion: c_longlong,
   payload: *mut SvBitVecVal,
 ) {
-  debug!("axi_read_indexed (channel_id={channel_id}, arid={arid}, araddr={araddr}, \
+  debug!("axi_read_indexed (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
   arlen={arlen}, arsize={arsize}, arburst={arburst}, arlock={arlock}, arcache={arcache}, \
   arprot={arprot}, arqos={arqos}, arregion={arregion})");
   let driver = &mut *(target as *mut Driver);
-  *(payload as *mut AxiReadIndexedPayload) = driver.axi_read_indexed();
+  let response = driver.axi_read_indexed(araddr as u32, arsize as u64);
+  fill_axi_read_payload(payload, driver.dlen, response);
 }
 
 #[no_mangle]

difftest/online_drive/src/drive.rs

@@ -45,20 +45,22 @@ impl Driver {
     }
   }
 
-  pub(crate) fn axi_read_high_bandwidth(&mut self, addr: u64, arsize: u64) -> AxiReadPayload {
+  pub(crate) fn axi_read_high_bandwidth(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
     // TODO:
+    let size = 1 << arsize;
     info!(
-      "[{}] axi_read_high_bandwidth (addr={addr}, size={})",
-      get_t(),
-      1 << arsize
+      "[{}] axi_read_high_bandwidth (addr={addr:#x}, size={size})",
+      get_t()
     );
-    let data: Vec<u8> = (0..1 << arsize).map(|i| self.shadow_mem[(addr + i) as usize]).collect();
-    AxiReadPayload { data, beats: 0 }
+    let data: Vec<u8> = (0..size).map(|i| self.shadow_mem[(addr + i) as usize]).collect();
+    AxiReadPayload { data }
   }
 
-  pub(crate) fn axi_read_indexed(&mut self) -> AxiReadIndexedPayload {
-    info!("[{}] axi_read_indexed", get_t());
-    unimplemented!()
+  pub(crate) fn axi_read_indexed(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
+    let size = 1 << arsize;
+    info!("[{}] axi_read_indexed (addr={addr:#x}, size={size})", get_t());
+    let data: Vec<u8> = (0..size).map(|i| self.shadow_mem[(addr + i) as usize]).collect();
+    AxiReadPayload { data }
   }
 
   pub(crate) fn watchdog(&mut self) -> u8 {

difftest/test_common/src/spike_runner.rs

@@ -118,7 +118,7 @@ impl SpikeRunner {
       }
       None => {
         debug!(
-          "SpikeStep: spike run scalar insn, (pc={:#x}, disasm={}, bits={:#x})",
+          "SpikeStep: spike run scalar insn (pc={:#x}, disasm={}, bits={:#x})",
           pc, disasm, insn_bits,
         );
         proc.func()