[rocketv] fix t1 connect(wip).

chipsalliance · Jul 26, 2024 · 0d951c8 · 0d951c8
1 parent 3f4c88b
commit 0d951c8
Showing 1 changed file with 21 additions and 13 deletions.
diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
@@ -1353,10 +1353,10 @@ class Rocket(val parameter: RocketParameter)
       t1IssueQueue.io.enq.bits.rs2Data := wbRegRS2
       t1.issue.valid := t1IssueQueue.io.deq.valid
       t1.issue.bits := t1IssueQueue.io.deq.bits
+      t1IssueQueue.io.deq.ready := t1.issue.ready
       // For each different retirements, it should maintain different scoreboard
-      val t1MemoryRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.mem.bits), maxCount))
-      val t1CSRRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.csr.bits), maxCount))
-      val t1XRDRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.rd.bits), maxCount))
+      val t1CSRRetireQueue: Queue[T1CSRRetire] = Module(new Queue(chiselTypeOf(t1.retire.csr.bits), maxCount))
+      val t1XRDRetireQueue: Queue[T1RdRetire] = Module(new Queue(chiselTypeOf(t1.retire.rd.bits), maxCount))
 
       val countWidth = log2Up(maxCount)
       def counterManagement(size: Int, margin: Int = 0)(grant: Bool, release: Bool, flush: Option[Bool] = None) = {
@@ -1373,26 +1373,34 @@ class Rocket(val parameter: RocketParameter)
         (empty, full)
       }
       // T1 Memory Scoreboard
-      val t1MemoryGrant:   Bool = t1.issue.valid && wbRegDecodeOutput(parameter.decoderParameter.vectorLSU)
+      val t1MemoryGrant:   Bool = t1IssueQueue.io.enq.valid && wbRegDecodeOutput(parameter.decoderParameter.vectorLSU)
       val t1MemoryRelease: Bool = t1.retire.mem.fire
-      val (lsuEmpty, _) = counterManagement(countWidth)(t1MemoryGrant, t1MemoryRelease)
+      // todo: handle vector lsu in pipe
+      // +1: There are instructions that will enter t1
+      val (lsuEmpty, _) = counterManagement(countWidth + 1)(t1MemoryGrant, t1MemoryRelease)
       // T1 CSR Scoreboard
-      val t1CSRGrant:   Bool = t1.issue.valid && wbRegDecodeOutput(???)
-      val t1CSRRelease: Bool = t1.retire.mem.fire
+      // todo: add wbRegDecodeOutput(vectorWriteCsr)
+      val t1CSRGrant:   Bool = false.B
+      val t1CSRRelease: Bool = false.B // t1CSRRetireQueue.io.deq.fire
+      val (t1CSREmpty, _) = counterManagement(countWidth + 1)(t1CSRGrant, t1CSRRelease)
       // T1 XRD Scoreboard?
 
       // Maintain vector counter
       // There may be 4 instructions in the pipe
-      val (vectorEmpty, vectorFull) = counterManagement(countWidth, 4)(t1.issue.valid, ???)
+      val (_, vectorFull) = counterManagement(countWidth, 4)(t1IssueQueue.io.enq.valid, t1.issue.fire)
       vectorLSUEmpty.foreach(_ := lsuEmpty)
       vectorQueueFull.foreach(_ := vectorFull)
 
-      val vectorTryToWriteRd = t1.retire.rd.valid && !t1.retire.rd.bits.isFp
-      val vectorTryToWriteFP = t1.retire.rd.valid && t1.retire.rd.bits.isFp
-      // TODO: maintain queue here?
+      t1XRDRetireQueue.io.enq.valid := t1.retire.rd.valid
+      t1XRDRetireQueue.io.enq.bits := t1.retire.rd.bits
+      t1CSRRetireQueue.io.enq.valid := t1.retire.csr.valid
+      t1CSRRetireQueue.io.enq.bits := t1.retire.csr.bits
+      // todo: write csr here
+      t1CSRRetireQueue.io.deq.ready := true.B
+
+      val vectorTryToWriteRd = t1XRDRetireQueue.io.deq.valid && !t1XRDRetireQueue.io.deq.bits.isFp
+      val vectorTryToWriteFP = t1XRDRetireQueue.io.deq.valid && t1XRDRetireQueue.io.deq.bits.isFp
       t1XRDRetireQueue.io.deq.ready := (!(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd) && (!(dmemResponseReplay && dmemResponseFpu) || !vectorTryToWriteFP)
-      t1CSRRetireQueue.io.deq.ready := (!(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd) && (!(dmemResponseReplay && dmemResponseFpu) || !vectorTryToWriteFP)
-      t1MemoryRetireQueue.io.deq.ready := (!(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd) && (!(dmemResponseReplay && dmemResponseFpu) || !vectorTryToWriteFP)
 
       when(t1.retire.rd.fire && vectorTryToWriteRd) {
         longlatencyWdata := t1.retire.rd.bits.rdData