[ipemu] fix ipemu

chipsalliance · Jul 10, 2024 · 0f32510 · 0f32510
1 parent 6216d67
commit 0f32510
Showing 1 changed file with 8 additions and 25 deletions.
diff --git a/ipemu/src/AXI4SlaveAgent.scala b/ipemu/src/AXI4SlaveAgent.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.ipemu.dpi
 
 // TODO: upstream to AMBA as VIP
 import chisel3._
-import chisel3.util.circt.dpi.{RawClockedNonVoidFunctionCall, RawClockedVoidFunctionCall}
+import chisel3.util.circt.dpi.{RawClockedVoidFunctionCall, RawUnlockedNonVoidFunctionCall}
 import chisel3.util.{OHToUInt, scanLeftOr}
 import org.chipsalliance.amba.axi4.bundle.{ARChannel, ARFlowControl, AWChannel, AWFlowControl, AXI4BundleParameter, AXI4ROIrrevocableVerilog, AXI4RWIrrevocableVerilog, AXI4WOIrrevocableVerilog, BChannel, BFlowControl, RChannel, RFlowControl, WChannel, WFlowControl}
 
@@ -152,22 +152,15 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
       val firstEmpty: UInt = OHToUInt(ffo(VecInit(cam.map(!_.valid)).asUInt))
       /** there are no outstanding read requests. */
       val camIsEmpty = VecInit(cam.map(content => !content.valid)).asUInt.andR
-      /** find oldest read. */
+      /** find oldest to index which cam to use. */
       val oldest = OHToUInt(ffo(VecInit(cam.map(content => content.valid)).asUInt))
-      /** index to select value from [[cam]]
-        * if cam empty, always select the next allocate value.
-        * if cam non-empty, update to oldest at each transaction end, this can be changed to random response with LFSR.
-        * @todo in the future, we can provide a fine-grand control to this index to provide out-of-order return.
-        */
-      val rIndex = RegInit(0.U.asTypeOf(UInt(16.W)))
 
       // AR
       channel.ARREADY := VecInit(cam.map(!_.valid)).asUInt.orR
       when(channel.ARREADY && channel.ARVALID) {
         cam(firstEmpty).arid := channel.ARID
         cam(firstEmpty).arlen := channel.ARLEN
-        cam(firstEmpty).readPayload := RawClockedNonVoidFunctionCall(s"axi_read_${parameter.name}", new ReadPayload(parameter.readPayloadSize, parameter.axiParameter.dataWidth))(
-          io.clock,
+        cam(firstEmpty).readPayload := RawUnlockedNonVoidFunctionCall(s"axi_read_${parameter.name}", new ReadPayload(parameter.readPayloadSize, parameter.axiParameter.dataWidth))(
           when.cond && !io.gateRead,
           io.channelId,
           channel.ARID.asTypeOf(UInt(64.W)),
@@ -186,27 +179,17 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
       }
 
       // R
-      rIndex := Mux(
-        camIsEmpty,
-        firstEmpty, // if cam empty, always select the next allocate value.
-        Mux(
-          channel.RREADY && channel.RVALID && channel.RLAST,
-          oldest, // if cam non-empty, update to oldest at each transaction end, this can be changed to random response with LFSR.
-          rIndex
-        )
-      )
-
       channel.RVALID := VecInit(cam.map(_.valid)).asUInt.orR
-      channel.RID := cam(rIndex).arid
-      channel.RDATA := cam(rIndex).readPayload.data(cam(rIndex).readPayloadIndex)
+      channel.RID := cam(oldest).arid
+      channel.RDATA := cam(oldest).readPayload.data(cam(oldest).readPayloadIndex)
       channel.RRESP := 0.U // OK
-      channel.RLAST := cam(rIndex).arlen === cam(rIndex).readPayloadIndex
+      channel.RLAST := (cam(oldest).arlen === cam(oldest).readPayloadIndex) && cam(oldest).valid
       channel.RUSER := DontCare
       when(channel.RREADY && channel.RVALID) {
         // increase index
-        cam(rIndex).readPayloadIndex := cam(rIndex).readPayloadIndex + 1.U
+        cam(oldest).readPayloadIndex := cam(oldest).readPayloadIndex + 1.U
         when(channel.RLAST) {
-          cam(rIndex).valid := false.B
+          cam(oldest).valid := false.B
         }
       }
     }