[soc] Handle vector writing to float registers.

chipsalliance · Apr 23, 2024 · 149bc2f · 149bc2f
1 parent 762d9b4
commit 149bc2f
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Showing 6 changed files with 32 additions and 6 deletions.
diff --git a/rocket/src/AbstractT1.scala b/rocket/src/AbstractT1.scala
@@ -41,6 +41,8 @@ class VectorResponse(xLen: Int) extends Bundle {
     */
   val rd: Valid[UInt] = Valid(UInt(log2Ceil(32).W))
 
+  val float: Bool = Bool()
+
   /** Vector Fixed-Point Saturation Flag, propagate to vcsr in CSR.
     * This is not maintained in the vector coprocessor since it is not used in the Vector processor.
     */

diff --git a/rocket/src/RocketCore.scala b/rocket/src/RocketCore.scala
@@ -973,8 +973,12 @@ class Rocket(flushOnFenceI: Boolean, hasBeu: Boolean)(implicit val p: Parameters
         .map {
           case (fpu, fpHazardTargets) =>
             val fpScoreboard = new Scoreboard(32)
-            fpScoreboard.set((wbDcacheMiss && wbRegDecodeOutput(decoder.wfd) || fpu.sboard_set) && wbValid, wbWaddr)
+            fpScoreboard.set(((wbDcacheMiss || wbRegDecodeOutput(decoder.vector)) && wbRegDecodeOutput(decoder.wfd) || fpu.sboard_set) && wbValid, wbWaddr)
             fpScoreboard.clear(dmemResponseReplay && dmemResponseFpu, dmemResponseWaddr)
+            t1Response.foreach { response =>
+              val vectorTryToWriteFP = response.bits.rd.valid && response.bits.float
+              fpScoreboard.clear(response.fire && vectorTryToWriteFP, response.bits.rd.bits)
+            }
             fpScoreboard.clear(fpu.sboard_clr, fpu.sboard_clra)
             checkHazards(fpHazardTargets, fpScoreboard.read)
         }
@@ -1129,13 +1133,25 @@ class Rocket(flushOnFenceI: Boolean, hasBeu: Boolean)(implicit val p: Parameters
     }
     // todo: vector change csr
     t1Response.foreach { vectorResponse =>
-      val vectorTryToWriteRd = vectorResponse.bits.rd.valid
-      vectorResponse.ready := !(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd
+      val vectorTryToWriteRd = vectorResponse.bits.rd.valid && !vectorResponse.bits.float
+      val vectorTryToWriteFP = vectorResponse.bits.rd.valid && vectorResponse.bits.float
+      vectorResponse.ready := (!(wbWxd || (dmemResponseReplay && dmemResponseXpu)) || !vectorTryToWriteRd) &&
+        (!(dmemResponseReplay && dmemResponseFpu) || !vectorTryToWriteFP)
       when(vectorResponse.fire && vectorTryToWriteRd) {
         longlatencyWdata := vectorResponse.bits.data
         longlatencyWaddress := vectorResponse.bits.rd.bits
         longLatencyWenable := true.B
       }
+      fpu.foreach { fpu =>
+        when(!(dmemResponseValid && dmemResponseFpu)) {
+          fpu.dmem_resp_val := vectorResponse.fire && vectorTryToWriteFP
+          fpu.dmem_resp_data := vectorResponse.bits.data
+          // todo: 32 bit only
+          fpu.dmem_resp_type := 2.U
+          // todo: connect tag
+          fpu.dmem_resp_tag := 0.U
+        }
+      }
     }
 
     dmem.req.valid := exRegValid && exRegDecodeOutput(decoder.mem)

diff --git a/subsystem/src/LazyT1.scala b/subsystem/src/LazyT1.scala
@@ -43,6 +43,7 @@ class LazyT1Imp(outer: LazyT1)(implicit p: Parameters) extends AbstractLazyT1Mod
   response.valid := t1.response.valid
   response.bits.data := t1.response.bits.data
   response.bits.rd := t1.response.bits.rd
+  response.bits.float := t1.response.bits.float
   response.bits.vxsat := t1.response.bits.vxsat
   response.bits.mem := t1.response.bits.mem
 

diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
@@ -44,6 +44,8 @@ class VResponse(xLen: Int) extends Bundle {
     */
   val rd: ValidIO[UInt] = Valid(UInt(log2Ceil(32).W))
 
+  val float: Bool = Bool()
+
   /** when [[mem]] is asserted, indicate the instruction need to access memory.
     * if the vector instruction need to access memory,
     * to maintain the order of memory access:

diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -632,6 +632,11 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
       val firstLaneIndex: UInt = OHToUInt(firstLane)(log2Ceil(parameter.laneNumber) - 1, 0)
       response.bits.rd.valid := lastSlotCommit && decodeResultReg(Decoder.targetRd)
       response.bits.rd.bits := vd
+      if (parameter.fpuEnable) {
+        response.bits.float := decodeResultReg(Decoder.float)
+      } else {
+        response.bits.float := false.B
+      }
       when(requestRegDequeue.fire) {
         ffoIndexReg.valid := false.B
         ffoIndexReg.bits := -1.S(parameter.xLen.W).asUInt

diff --git a/t1/src/decoder/Decoder.scala b/t1/src/decoder/Decoder.scala
@@ -278,8 +278,9 @@ object Decoder {
       val isFFO = ffo.value(op)
       // extend read only
       val extendType = Seq(mv, popCount, id)
+      val isMVtoFP = op.special.isDefined && op.special.get.name == "VWFUNARY0"
       val isOtherType: Boolean =
-        (Seq(isGather, isMerge, isClip, isFFO) ++ extendType.map(_.value(op))).reduce(_ || _)
+        !isMVtoFP && (Seq(isGather, isMerge, isClip, isFFO) ++ extendType.map(_.value(op))).reduce(_ || _)
       // ++ffo
       val otherType = Seq(isGather, isMerge, isClip) ++ extendType.map(_.value(op))
       val typeIndex = if (otherType.contains(true)) 4 + otherType.indexOf(true) else 0
@@ -301,8 +302,7 @@ object Decoder {
       !(
         other.value(op) ||
           dontNeedExecuteInLane.value(op) ||
-          slid.value(op) ||
-          mv.value(op) || divider.value(op))
+          slid.value(op) || divider.value(op))
   }
 
   object floatConvertUnsigned extends BoolField {