[difftest] add chisel fatal check when simulation quit

chipsalliance · Jul 28, 2024 · 1c188cb · 1c188cb
1 parent 92e5311
commit 1c188cb
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Showing 3 changed files with 22 additions and 1 deletion.
diff --git a/difftest/online_drive/dpi_c/dpi_pre_link.cc b/difftest/online_drive/dpi_c/dpi_pre_link.cc
@@ -6,6 +6,12 @@ class VTestBench;
 static VerilatedContext *contextp;
 static VTestBench *topp;
 
+bool stop;
+
+extern "C" void simulation_stop_c() {
+  stop = true;
+}
+
 extern "C" int verilator_main_c(int argc, char **argv) {
   // Setup context, defaults, and parse command line
   Verilated::debug(0);
@@ -19,6 +25,9 @@ extern "C" int verilator_main_c(int argc, char **argv) {
   // Construct the Verilated model, from Vtop.h generated from Verilating
   topp = new VTestBench(contextp);
 
+  // Set the simulation stop flag
+  stop = false;
+
   // Simulate until $finish
   while (!contextp->gotFinish()) {
     // Evaluate model
@@ -29,7 +38,8 @@ extern "C" int verilator_main_c(int argc, char **argv) {
     contextp->time(topp->nextTimeSlot());
   }
 
-  if (!contextp->gotFinish()) {
+  // If $finish is not called or stop with fatal error
+  if (!contextp->gotFinish() || !stop) { 
     VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
   }
 

diff --git a/difftest/online_drive/src/dpi.rs b/difftest/online_drive/src/dpi.rs
@@ -262,6 +262,14 @@ unsafe extern "C" fn retire_vector_mem(dummy: *const SvBitVecVal) {
   driver.retire_memory();
 }
 
+#[no_mangle]
+unsafe extern "C" fn simulation_stop() {
+  unsafe {
+    simulation_stop_c();
+  }
+}
+
+
 //--------------------------------
 // import functions and wrappers
 //--------------------------------
@@ -274,6 +282,8 @@ extern "C" {
   fn dump_wave_c(path: *const c_char);
 
   fn get_t_c() -> u64;
+
+  fn simulation_stop_c();
 }
 
 pub(crate) fn get_t() -> u64 {

diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala
@@ -130,6 +130,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
   dut.io.issue.bits.vstart := issue.vstart
   dut.io.issue.bits.vcsr := issue.vcsr
   dut.io.issue.valid := issue.meta === 1.U
+  RawClockedVoidFunctionCall("simulation_stop")(clock, issue.meta =/= 0.U && issue.meta =/= 1.U && issue.meta =/= 2.U)
   when(issue.meta =/= 0.U && issue.meta =/= 1.U && issue.meta =/= 2.U) {
     stop(cf"""{"event":"SimulationStop","reason": ${issue.meta},"cycle":${simulationTime}}\n""")
   }