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[t1rocket] remove rd check because of the repeatition with regwrite
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@Clo91eaf
Clo91eaf committed Aug 19, 2024
1 parent 65f710b commit 2eace1c
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Showing 5 changed files with 29 additions and 80 deletions.
4 changes: 0 additions & 4 deletions t1rocketemu/offline/src/difftest.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -78,10 +78,6 @@ impl Difftest {
cycle: *cycle,
})
}
JsonEvents::CheckRd { data, issue_idx, cycle } => {
self.runner.cycle = *cycle;
self.runner.check_rd(&CheckRdEvent { data: *data, issue_idx: *issue_idx, cycle: *cycle })
}
JsonEvents::VrfScoreboard { count, issue_idx, cycle } => {
self.runner.cycle = *cycle;
self.runner.vrf_scoreboard(&VrfScoreboardEvent {
Expand Down
62 changes: 19 additions & 43 deletions t1rocketemu/offline/src/json_events.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -90,12 +90,6 @@ pub(crate) enum JsonEvents {
address: u32,
cycle: u64,
},
CheckRd {
#[serde(deserialize_with = "str_to_u32", default)]
data: u32,
issue_idx: u8,
cycle: u64,
},
VrfScoreboard {
count: u32,
issue_idx: u8,
Expand Down Expand Up @@ -143,12 +137,6 @@ pub struct VrfScoreboardEvent {
pub cycle: u64,
}

pub struct CheckRdEvent {
pub data: u32,
pub issue_idx: u8,
pub cycle: u64,
}

pub(crate) trait JsonEventRunner {
fn peek_reg_write(&mut self, reg_write: &RegWriteEvent) -> anyhow::Result<()>;

Expand All @@ -164,8 +152,6 @@ pub(crate) trait JsonEventRunner {

fn check_and_clear_fence(&mut self);

fn check_rd(&mut self, check_rd: &CheckRdEvent) -> anyhow::Result<()>;

fn retire(&mut self, cycle: u64, issue_idx: u8) -> anyhow::Result<()>;
}

Expand All @@ -175,17 +161,27 @@ impl JsonEventRunner for SpikeRunner {
let idx = reg_write.idx;
let data = reg_write.data;

let se = self.find_rf_se();
let se = self.find_reg_write_se();

info!(
"[{cycle}] RegWrite: rtl idx={idx}, data={data:08x}; se idx={}, data={:08x} ({})",
"[{cycle}] RegWrite: rtl idx={idx}, data={data:#08x}; se idx={}, data={:#08x} ({})",
se.rd_idx,
se.rd_bits,
se.describe_insn()
);

assert!(idx as u32 == se.rd_idx, "rtl idx({:#x}) should be equal to spike idx({:#x})", idx, se.rd_idx);
assert!(data == se.rd_bits, "rtl data({:#x}) should be equal to spike data({:#x})", data, se.rd_bits);
assert!(
idx as u32 == se.rd_idx,
"rtl idx({:#x}) should be equal to spike idx({:#x})",
idx,
se.rd_idx
);
assert!(
data == se.rd_bits,
"rtl data({:#x}) should be equal to spike data({:#x})",
data,
se.rd_bits
);

Ok(())
}
Expand Down Expand Up @@ -274,7 +270,7 @@ impl JsonEventRunner for SpikeRunner {
assert_eq!(
record.byte,
written_byte,
"[{}] {offset}th byte incorrect ({:02x} record != {written_byte:02x} written) \
"[{}] {offset}th byte incorrect ({:#02x} record != {written_byte:#02x} written) \
for vrf write (lane={}, vd={}, offset={}, mask={}, data={:x?}) \
issue_idx={} [vrf_idx={}] (disasm: {}, pc: {:#x}, bits: {:#x})",
vrf_write.cycle,
Expand Down Expand Up @@ -328,7 +324,7 @@ impl JsonEventRunner for SpikeRunner {
let lsu_idx = memory_write.lsu_idx;

if let Some(se) = self.commit_queue.iter_mut().find(|se| se.lsu_idx == lsu_idx) {
info!("[{cycle}] MemoryWrite: address={base_addr:08x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm);
info!("[{cycle}] MemoryWrite: address={base_addr:#08x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm);
// compare with spike event record
mask.iter().enumerate()
.filter(|(_, &mask)| mask)
Expand All @@ -337,11 +333,11 @@ impl JsonEventRunner for SpikeRunner {
let data_byte = *data.get(offset).unwrap_or(&0);
let mem_write =
se.mem_access_record.all_writes.get_mut(&byte_addr).unwrap_or_else(|| {
panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:08x}")
panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:#08x}")
});
let single_mem_write_val = mem_write.writes[mem_write.num_completed_writes].val;
mem_write.num_completed_writes += 1;
assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:02X}, actual byte {data_byte:02X} (byte_addr={byte_addr:08X}, pc = {:#x}, disasm = {})", se.pc, se.disasm);
assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:#02x}, actual byte {data_byte:#02x} (byte_addr={byte_addr:#08x}, pc = {:#x}, disasm = {})", se.pc, se.disasm);
});
return Ok(());
}
Expand All @@ -363,8 +359,7 @@ impl JsonEventRunner for SpikeRunner {
se.vrf_access_record.retired_writes, se.describe_insn()
);

// if instruction writes rd, it will retire in check_rd()
if count == se.vrf_access_record.retired_writes && !se.is_rd_written {
if count == se.vrf_access_record.retired_writes {
should_retire = Some(issue_idx);
}
// if all writes are committed, retire the se
Expand Down Expand Up @@ -397,25 +392,6 @@ impl JsonEventRunner for SpikeRunner {
}
}

fn check_rd(&mut self, check_rd: &CheckRdEvent) -> anyhow::Result<()> {
let data = check_rd.data;
let cycle = check_rd.cycle;
let issue_idx = check_rd.issue_idx;

let se =
self.commit_queue.iter_mut().find(|se| se.issue_idx == issue_idx).unwrap_or_else(|| {
panic!("[{cycle}] cannot find se with instruction issue_idx={issue_idx}")
});

info!("[{cycle}] CheckRd: issue_idx={issue_idx}, data={data:x?}");

se.check_rd(data).expect("Failed to check_rd");

self.retire(cycle, issue_idx).unwrap();

Ok(())
}

fn retire(&mut self, cycle: u64, issue_idx: u8) -> anyhow::Result<()> {
if let Some(idx) = self.commit_queue.iter().position(|se| se.issue_idx == issue_idx) {
if let Some(se) = self.commit_queue.remove(idx) {
Expand Down
30 changes: 7 additions & 23 deletions t1rocketemu/spike_rs/src/spike_event.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -325,18 +325,15 @@ impl SpikeEvent {

pub fn pre_log_arch_changes(&mut self, spike: &Spike, vlen: u32) -> anyhow::Result<()> {
if self.do_log_vrf {
self.rd_bits = spike.get_proc().get_rd();

// record the vrf writes before executing the insn
let vlen_in_bytes = vlen;

let proc = spike.get_proc();
let (start, len) = self.get_vrf_write_range(vlen_in_bytes).unwrap();
self.rd_bits = proc.get_state().get_reg(self.rd_idx, false);
let (start, len) = self.get_vrf_write_range(vlen).unwrap();
self.vd_write_record.vd_bytes.resize(len as usize, 0u8);
for i in 0..len {
let offset = start + i;
let vreg_index = offset / vlen_in_bytes;
let vreg_offset = offset % vlen_in_bytes;
let vreg_index = offset / vlen;
let vreg_offset = offset % vlen;
let cur_byte = proc.get_vreg_data(vreg_index, vreg_offset);
self.vd_write_record.vd_bytes[i as usize] = cur_byte;
}
Expand Down Expand Up @@ -412,7 +409,7 @@ impl SpikeEvent {
self.is_rd_written = true;
self.rd_bits = data;
trace!(
"ScalarRFChange: idx={:02x}, data={:08x}",
"ScalarRFChange: idx={:#02x}, data={:08x}",
self.rd_idx,
self.rd_bits
);
Expand All @@ -424,13 +421,13 @@ impl SpikeEvent {
self.is_rd_written = true;
self.rd_bits = data;
trace!(
"FloatRFChange: idx={:02x}, data={:08x}",
"FloatRFChange: idx={:#02x}, data={:08x}",
self.rd_idx,
self.rd_bits
);
}
_ => trace!(
"UnknownRegChange, idx={:02x}, spike detect unknown reg change",
"UnknownRegChange, idx={:#02x}, spike detect unknown reg change",
self.rd_idx
),
}
Expand Down Expand Up @@ -494,19 +491,6 @@ impl SpikeEvent {
Ok(())
}

pub fn check_rd(&self, data: u32) -> anyhow::Result<()> {
// TODO: rtl should indicate whether resp_bits_data is valid
if self.is_rd_written {
assert_eq!(
data, self.rd_bits,
"expect to write rd[{}] = {}, actual {}",
self.rd_idx, self.rd_bits, data
);
}

Ok(())
}

pub fn check_is_ready_for_commit(&self, cycle: u64) -> anyhow::Result<()> {
for (addr, record) in &self.mem_access_record.all_writes {
assert_eq!(
Expand Down
7 changes: 0 additions & 7 deletions t1rocketemu/src/TestBench.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -249,13 +249,6 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
printf(cf"""{"event":"Issue","idx":${t1Probe.issue.bits},"cycle":${simulationTime}}\n""")
)

// t1 retire
when(t1Probe.retire.valid)(
printf(
cf"""{"event":"CheckRd","data":"${t1Probe.retire.bits}%x","issue_idx":${t1Probe.responseCounter},"cycle":${simulationTime}}\n"""
)
)

// t1 lsu enq
when(t1Probe.lsuProbe.reqEnq.orR)(
printf(cf"""{"event":"LsuEnq","enq":${t1Probe.lsuProbe.reqEnq},"cycle":${simulationTime}}\n""")
Expand Down
6 changes: 3 additions & 3 deletions t1rocketemu/test_common/src/spike_runner.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -128,15 +128,15 @@ impl SpikeRunner {
event
}

pub fn find_rf_se(&mut self) -> SpikeEvent {
pub fn find_reg_write_se(&mut self) -> SpikeEvent {
if !self.scalar_queue.is_empty() {
// return the back (oldest) scalar insn
self.scalar_queue.pop_back().unwrap()
} else {
// else, loop until find a se, and push the se to the front
loop {
let se = self.spike_step();
if se.is_scalar() && se.is_rd_written && se.rd_idx != 0 {
if se.is_rd_written && se.rd_idx != 0 {
return se;
} else if se.is_v() {
self.vector_queue.push_front(se.clone());
Expand All @@ -153,7 +153,7 @@ impl SpikeRunner {
// else, loop until find a se, and push the se to the front
loop {
let se = self.spike_step();
if se.is_scalar() && se.is_rd_written && se.rd_idx != 0 {
if se.is_rd_written && se.rd_idx != 0 {
self.scalar_queue.push_front(se.clone());
} else if se.is_v() {
return se;
Expand Down

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