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[ipemu] should observe all memory write
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sequencer committed Jul 12, 2024
1 parent 7dde51d commit 35ce5b2
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Showing 3 changed files with 14 additions and 3 deletions.
6 changes: 4 additions & 2 deletions difftest/online_drive/src/dpi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,8 @@ unsafe extern "C" fn axi_write_highBandwidthPort_rs(
awlen={awlen}, awsize={awsize}, awburst={awburst}, awlock={awlock}, awcache={awcache}, \
awprot={awprot}, awqos={awqos}, awregion={awregion})"
);
// nothing required to drive a write request
let driver = &mut *(target as *mut Driver);
driver.axi_write_high_bandwidth();
}

#[no_mangle]
Expand Down Expand Up @@ -163,7 +164,8 @@ unsafe extern "C" fn axi_write_indexedAccessPort_rs(
awlen={awlen}, awsize={awsize}, awburst={awburst}, awlock={awlock}, awcache={awcache}, \
awprot={awprot}, awqos={awqos}, awregion={awregion})"
);
// nothing required to drive a write request
let driver = &mut *(target as *mut Driver);
driver.axi_write_indexedAccessPort();
}

#[no_mangle]
Expand Down
9 changes: 9 additions & 0 deletions difftest/online_drive/src/drive.rs
Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,10 @@ impl Driver {
AxiReadPayload { data }
}

pub(crate) fn axi_write_high_bandwidth() {
unimplemented!();
}

pub(crate) fn axi_read_indexed(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
let size = 1 << arsize;
assert!(size <= 4);
Expand All @@ -102,6 +106,10 @@ impl Driver {
AxiReadPayload { data }
}

pub(crate) fn axi_write_indexed() {
unimplemented!();
}

pub(crate) fn watchdog(&mut self) -> u8 {
if get_t() - self.last_commit_cycle > self.timeout {
error!(
Expand Down Expand Up @@ -182,6 +190,7 @@ impl Driver {
);

// we make a copy of mem_access_record to circumvent the borrow checker
// todo: filter all vector instruction.
let mem_access_record = se_to_retire.mem_access_record.to_owned();
self.apply_to_shadow_mem(&mem_access_record);

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2 changes: 1 addition & 1 deletion ipemu/src/TestBench.scala
Original file line number Diff line number Diff line change
Expand Up @@ -143,7 +143,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
agent.io.reset := reset
agent.io.channelId := index.U
agent.io.gateRead := false.B
agent.io.gateWrite := true.B
agent.io.gateWrite := false.B
}

// Events for difftest and performance modeling
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