[rocketv] Reorder rf writes in tb.

chipsalliance · Aug 16, 2024 · 49074a2 · 49074a2
1 parent 3a5bcb5
commit 49074a2
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Showing 2 changed files with 41 additions and 26 deletions.
diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
@@ -24,12 +24,12 @@ class RocketROB(param: RocketParameter) extends Bundle {
   val commit: Bool = Bool()
   val trace: RocketRF = new RocketRF(param)
   val shouldWb: Bool = Bool()
-  val hasWb: Bool = Bool()
-  val tag: UInt = UInt(param.xLen.W)
+  val tag: UInt = UInt(5.W)
+  val wbSetScoreboard: Bool = Bool()
+  val longLatencyWrite: Bool = Bool()
 }
 
 class RocketProbe(param: RocketParameter) extends Bundle {
-  val trace: RocketRF = new RocketRF(param)
   val rob: RocketROB = new RocketROB(param)
   // rocket is idle
   val idle: Bool = Bool()
@@ -1081,15 +1081,15 @@ class Rocket(val parameter: RocketParameter)
     )
     when(rfWen) { rf.write(rfWaddr, rfWdata) }
 
-    probeWire.trace.rfWen := rfWen
-    probeWire.trace.rfWaddr := rfWaddr
-    probeWire.trace.rfWdata := rfWdata
+    probeWire.rob.trace.rfWen := rfWen
+    probeWire.rob.trace.rfWaddr := rfWaddr
+    probeWire.rob.trace.rfWdata := rfWdata
     // FIXME: vectorCSR
     probeWire.rob.commit := wbValid
-    probeWire.rob.trace := probeWire.trace
-    probeWire.rob.shouldWb := (wbRegDecodeOutput(parameter.decoderParameter.wfd) || (wbWxd && wbWaddr =/= 0.U)) && !wbException
-    probeWire.rob.hasWb := wbWxd && wbWen // FIXME: && !wb_set_sboard
-    probeWire.rob.tag := wbWaddr + Mux(wbRegDecodeOutput(parameter.decoderParameter.wfd), 32.U, 0.U)
+    probeWire.rob.shouldWb := wbWxd && wbWaddr =/= 0.U && !wbException
+    probeWire.rob.tag := wbWaddr
+    probeWire.rob.wbSetScoreboard := wbSetSboard && wbWen
+    probeWire.rob.longLatencyWrite := longLatencyWenable
 
     // hook up control/status regfile
     csr.io.ungatedClock := io.clock
@@ -1443,12 +1443,11 @@ class Rocket(val parameter: RocketParameter)
       }
       io.fpu.foreach { fpu =>
         when(!(dmemResponseValid && dmemResponseFpu)) {
-          fpu.dmem_resp_val := t1.retire.mem.fire && vectorTryToWriteFP
-          fpu.dmem_resp_data := t1.retire.rd.bits.rdData
+          fpu.dmem_resp_val := t1XRDRetireQueue.io.deq.valid && vectorTryToWriteFP
+          fpu.dmem_resp_data := t1XRDRetireQueue.io.deq.bits.rdData
           // todo: 32 bit only
           fpu.dmem_resp_type := 2.U
-          // todo: connect tag
-          fpu.dmem_resp_tag := 0.U
+          fpu.dmem_resp_tag := t1XRDRetireQueue.io.deq.bits.rdAddress
         }
       }
     }

diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
@@ -7,8 +7,9 @@ import chisel3._
 import chisel3.experimental.{BaseModule, ExtModule, SerializableModuleGenerator}
 import chisel3.experimental.dataview.DataViewable
 import chisel3.util.circt.dpi.{RawClockedNonVoidFunctionCall, RawUnclockedNonVoidFunctionCall}
-import chisel3.util.{HasExtModuleInline, PopCount, UIntToOH, Valid}
+import chisel3.util.{HasExtModuleInline, Mux1H, PopCount, Queue, UIntToOH, Valid}
 import org.chipsalliance.amba.axi4.bundle._
+import org.chipsalliance.rocketv.RocketROB
 import org.chipsalliance.t1.t1rocketemu.dpi._
 import org.chipsalliance.t1.tile.{T1RocketTile, T1RocketTileParameter}
 
@@ -176,25 +177,40 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
 
   // output the probes
   // rocket reg write rob
-
-  // FIXME: just fake code, wip
-  val robQueue = Module(new Queue(new RocketROB(generator.parameter.rocketParameter), 16))
+  val robQueue = Module(new Queue(new RocketROB(generator.parameter.rocketParameter), 32))
+  val robWriteDataValid = RegInit(0.U(32.W))
+  val robWriteData: Vec[UInt] = VecInit(Seq.tabulate(32){ _ => RegInit(0.U(generator.parameter.xLen.W))})
   // push queue
-  robQueue.io.enq.valid := rocketProbe.rob.commit
+  robQueue.io.enq.valid := rocketProbe.rob.commit && rocketProbe.rob.shouldWb
   robQueue.io.enq.bits := rocketProbe.rob
 
-  // modify rob trace
-  robQueue.foreach { elem =>
-    when(elem.tag == rocketProbe.trace.rfWaddr && rocketProbe.trace.rfWen) {
-      elem.trace := rocketProbe.trace
+  // update rob write
+  val LatencyWrite: Bool = rocketProbe.rob.longLatencyWrite
+  val doEnqSelect: UInt = Mux(rocketProbe.rob.longLatencyWrite, UIntToOH(rocketProbe.rob.trace.rfWaddr), 0.U(32.W))
+  val doDeqSelect = Wire(UInt(32.W))
+  robWriteDataValid := (doEnqSelect | robWriteDataValid) & (~doDeqSelect).asUInt
+  when(LatencyWrite) {
+    robWriteData.zip(doEnqSelect.asBools).foreach {case (d, s) =>
+      d := Mux(s, rocketProbe.rob.trace.rfWdata, d)
     }
   }
 
   // pop queue and output trace
-  robQueue.io.deq.ready := robQueue.last.valid // fixme
-  when(robQueue.io.deq.fire && robQueue.io.deq.bits.rob.trace.rfWen && robQueue.io.deq.bits.rob.trace.rfWaddr =/= 0.U)(
+  val deqLongLatency: Bool = robQueue.io.deq.bits.wbSetScoreboard
+  robQueue.io.deq.ready :=
+    // Normal writing
+    !deqLongLatency ||
+      // Long latency data is ready
+      (robWriteDataValid & UIntToOH(robQueue.io.deq.bits.tag)).orR
+  val writeData: UInt = Mux(
+    deqLongLatency,
+    Mux1H(UIntToOH(robQueue.io.deq.bits.tag), robWriteData),
+    robQueue.io.deq.bits.trace.rfWdata
+  )
+  doDeqSelect := Mux(robQueue.io.deq.fire && deqLongLatency, UIntToOH(robQueue.io.deq.bits.tag), 0.U(32.W))
+  when(robQueue.io.deq.fire)(
     printf(
-      cf"""{"event":"RegWrite","idx":${robQueue.io.deq.bits.rob.trace.rfWaddr},"data":"${robQueue.io.deq.bits.rob.trace.rfWdata}%x","cycle":${simulationTime}}\n"""
+      cf"""{"event":"RegWrite","idx":${robQueue.io.deq.bits.tag},"data":"${writeData}%x","cycle":${simulationTime}}\n"""
     )
   )