[rtl] get topUop.

chipsalliance · Jun 13, 2024 · 4e7483f · 4e7483f
1 parent da298a3
commit 4e7483f
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Showing 3 changed files with 15 additions and 17 deletions.
diff --git a/t1/src/decoder/Decoder.scala b/t1/src/decoder/Decoder.scala
@@ -5,11 +5,10 @@ package org.chipsalliance.t1.rtl.decoder
 
 import chisel3._
 import chisel3.util.BitPat
-import chisel3.util.experimental.decode.{BoolDecodeField, DecodeBundle, DecodeField, DecodePattern, DecodeTable}
-import org.chipsalliance.rvdecoderdb
-import org.chipsalliance.rvdecoderdb.{Encoding, Instruction, InstructionSet}
+import chisel3.util.experimental.decode._
+import org.chipsalliance.rvdecoderdb.Instruction
 import org.chipsalliance.t1.rtl.T1Parameter
-import org.chipsalliance.t1.rtl.decoder.attribute.{AdderUOPType, DivUOPType, FUT0, FUT1, FUT10, FUT12, FUT13, FUT14, FUT2, FUT3, FUT4, FUT5, FUT6, FUT7, FUT8, FUT9, FloatUopType, FpExecutionType, LogicUopType, MulUOPType, OtherUopType, ShiftUopType, T0, T1, T10, T11, T2, T3, T4, T6, T7, T8, T9, TopUop, TopUopType, TriState, addUop0, addUop1, addUop10, addUop11, addUop2, addUop3, addUop4, addUop6, addUop7, addUop8, addUop9, divUop0, divUop1, divUop10, divUop8, divUop9, logicUop0, logicUop1, logicUop2, logicUop4, logicUop5, logicUop6, logicUop8, logicUop9, mulUop0, mulUop1, mulUop10, mulUop14, mulUop3, mulUop5, otherUop0, otherUop1, otherUop2, otherUop3, otherUop4, otherUop5, otherUop6, otherUop7, otherUop8, otherUop9, shiftUop0, shiftUop1, shiftUop2, shiftUop4, shiftUop6}
+import org.chipsalliance.t1.rtl.decoder.attribute._
 
 trait T1DecodeFiled[D <: Data] extends DecodeField[T1DecodePattern, D] with FieldName
 
@@ -209,7 +208,14 @@ object orderReduce extends T1BoolField {
 }
 
 object topUop extends T1UopField {
-  override def genTable(pattern: T1DecodePattern): BitPat = pattern.topUop match {
+  override def genTable(pattern: T1DecodePattern): BitPat = pattern.topUop.value match {
+    case TopT0 => BitPat("b0000")
+    case TopT1 => BitPat("b0001")
+    case TopT2 => BitPat("b0010")
+    case TopT3 => BitPat("b0011")
+    case TopT5 => BitPat("b0101")
+    case TopT6 => BitPat("b0110")
+    case TopT7 => BitPat("b0111")
     case _ => BitPat.dontCare(4)
   }
 }

diff --git a/t1/src/decoder/T1DecodePattern.scala b/t1/src/decoder/T1DecodePattern.scala
@@ -112,7 +112,7 @@ case class T1DecodePattern(instruction: Instruction, t1Parameter: T1Parameter) e
   def isVwmacc: isVwmacc = attribute.isVwmacc(this)
   def isWidenreduce: isWidenreduce = attribute.isWidenreduce(this)
   def fpExecutionType: FpExecutionType.Type = attribute.FpExecutionType(this)
-  def topUop: TopUopType = attribute.TopUop(this)
+  def topUop: TopUop = attribute.TopUop(this)
   def decoderUop: DecoderUop = attribute.DecoderUop(this)
 
   private def documentation: String = InstructionDocumentation(instruction, t1Parameter).toString

diff --git a/t1/src/decoder/attribute/topUop.scala b/t1/src/decoder/attribute/topUop.scala
@@ -10,38 +10,32 @@ object TopT0 extends TopUopType
 object TopT1 extends TopUopType
 object TopT2 extends TopUopType
 object TopT3 extends TopUopType
-object TopT4 extends TopUopType
 object TopT5 extends TopUopType
 object TopT6 extends TopUopType
 object TopT7 extends TopUopType
-object TopDC extends TopUopType
 
 object TopUop {
-  def apply(t1DecodePattern: T1DecodePattern): TopUopType = {
+  def apply(t1DecodePattern: T1DecodePattern): TopUop = {
     Seq(
       t0 _ -> TopT0,
       t1 _ -> TopT1,
       t2 _ -> TopT2,
       t3 _ -> TopT3,
-      t4 _ -> TopT4,
       t5 _ -> TopT5,
       t6 _ -> TopT6,
       t7 _ -> TopT7,
-      dc _ -> TopDC,
     ).collectFirst {
-      case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe)
-    }.get
+      case (fn, tpe) if fn(t1DecodePattern) => TopUop(tpe)
+    }.getOrElse(TopUop(TopT0))
   }
   def t0(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i =>
       !(t1(t1DecodePattern) 
         || t2(t1DecodePattern)
         || t3(t1DecodePattern)
-        || t4(t1DecodePattern)
         || t5(t1DecodePattern)
         || t6(t1DecodePattern)
         || t7(t1DecodePattern)
-        || dc(t1DecodePattern)
       )
     )
     allMatched.contains(t1DecodePattern.instruction.name)
@@ -70,7 +64,6 @@ object TopUop {
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
-  def t4(t1DecodePattern: T1DecodePattern): Boolean = false
   def t5(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
       "vsext.vf2",
@@ -89,7 +82,6 @@ object TopUop {
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
-  def dc(t1DecodePattern: T1DecodePattern): Boolean = false
 }
 
 case class TopUop(value: TopUopType) extends UopDecodeAttribute[TopUopType] {