[rtl] fix ffo pipe.

chipsalliance · Dec 26, 2024 · 5722f41 · 5722f41
1 parent b1245cc
commit 5722f41
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Showing 2 changed files with 12 additions and 5 deletions.
diff --git a/t1/src/mask/MaskCompress.scala b/t1/src/mask/MaskCompress.scala
@@ -54,6 +54,7 @@ class MaskCompressInterFace(parameter: CompressParam) extends Bundle {
   val newInstruction: Bool                   = Input(Bool())
   val ffoInstruction: Bool                   = Input(Bool())
   val writeData:      UInt                   = Output(UInt(parameter.xLen.W))
+  val stageValid:     Bool                   = Bool()
   val om = Output(Property[AnyClassType]())
 }
 
@@ -239,10 +240,13 @@ class MaskCompress(val parameter: CompressParam)
   )
   compressMask := Mux(compressTailValid, compressTailMask, (-1.S(out.mask.getWidth.W)).asUInt)
 
+  val validInputPipe     = initRegEnable(in.bits.validInput, in.fire)
+  val readFromScalarPipe = initRegEnable(in.bits.readFromScalar, in.fire)
+
   val mvMask = Mux1H(eew1H, Seq(1.U, 3.U, 15.U))
-  val mvData = in.bits.readFromScalar
+  val mvData = readFromScalarPipe
 
-  val ffoMask: UInt = FillInterleaved(parameter.datapathWidth / 8, in.bits.validInput)
+  val ffoMask: UInt = FillInterleaved(parameter.datapathWidth / 8, validInputPipe)
 
   outWire.data := Mux1H(
     Seq(
@@ -303,6 +307,8 @@ class MaskCompress(val parameter: CompressParam)
   }.elsewhen(mvRd) {
     ffoIndex := source1SigExtend
   }
-  outWire.ffoOutput := completedLeftOr | Fill(parameter.laneNumber, ffoValid)
-  out := RegNext(outWire, 0.U.asTypeOf(outWire))
+  val ffoOutPipe:      UInt = initRegEnable(completedLeftOr | Fill(parameter.laneNumber, ffoValid), in.fire)
+  outWire.ffoOutput := ffoOutPipe
+  out               := RegNext(outWire, 0.U.asTypeOf(outWire))
+  io.stageValid     := stage2Valid
 }
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -1137,7 +1137,8 @@ class MaskUnit(val parameter: T1Parameter)
   // todo: token
   val waiteLastRequest: Bool = RegInit(false.B)
   val waitQueueClear:   Bool = RegInit(false.B)
-  val lastReportValid = waitQueueClear && !writeQueue.map(_.deq.valid).reduce(_ || _) && dataNotInShifter
+  val lastReportValid = waitQueueClear && !writeQueue.map(_.deq.valid).reduce(_ || _) &&
+    dataNotInShifter && !compressUnit.io.stageValid
   when(lastReportValid) {
     waitQueueClear   := false.B
     waiteLastRequest := false.B