Merge branch 'supp-zvbb' of github.com:chipsalliance/t1 into supp-zvbb

build.sc

@@ -20,7 +20,7 @@ object v {
   val scala = "2.13.14"
   val mainargs = ivy"com.lihaoyi::mainargs:0.5.0"
   val oslib = ivy"com.lihaoyi::os-lib:0.9.1"
-  val upickle = ivy"com.lihaoyi::upickle:3.1.3"
+  val upickle = ivy"com.lihaoyi::upickle:3.3.1"
   val spire = ivy"org.typelevel::spire:latest.integration"
   val evilplot = ivy"io.github.cibotech::evilplot:latest.integration"
 }

nix/pkgs/rvv-codegen.nix

@@ -11,10 +11,10 @@ buildGoModule {
   pname = "riscv-vector-test";
   version = "unstable-2023-04-12";
   src = fetchFromGitHub {
-    owner = "ksco";
+    owner = "chipsalliance";
     repo = "riscv-vector-tests";
-    rev = "bafa717d37b9bef3e80b66a50b01c22f532306bc";
-    hash = "sha256-C91HUDyMykS3qM9h+rJ2uKAJcKHkoakw9I+wwtco0m8=";
+    rev = "caae5c8fcf465be73266f9b3bd672f71a362548e";
+    hash = "sha256-388MKOO+g4PjR3BcxiA8vNY7itDcIhz88vZmMZkbsj8=";
   };
   doCheck = false;
   vendorHash = "sha256-9cQlivpHg6IDYpmgBp34n6BR/I0FIYnmrXCuiGmAhNE=";

nix/t1/_sources/generated.json

@@ -19,9 +19,29 @@
         },
         "version": "4a81e23e1794844b36c53385d343475d4d7eca49"
     },
+    "berkeley-hardfloat": {
+        "cargoLocks": null,
+        "date": "2024-06-05",
+        "extract": null,
+        "name": "berkeley-hardfloat",
+        "passthru": null,
+        "pinned": false,
+        "src": {
+            "deepClone": false,
+            "fetchSubmodules": false,
+            "leaveDotGit": false,
+            "name": null,
+            "owner": "ucb-bar",
+            "repo": "berkeley-hardfloat",
+            "rev": "26f00d00c3f3f57480065e02bfcfde3d3b41ec51",
+            "sha256": "sha256-gA1Ol7xnzC+10lGwK9+ftfJcMhKsC0KhjENQvUg3u88=",
+            "type": "github"
+        },
+        "version": "26f00d00c3f3f57480065e02bfcfde3d3b41ec51"
+    },
     "chisel": {
         "cargoLocks": null,
-        "date": "2024-07-12",
+        "date": "2024-07-25",
         "extract": null,
         "name": "chisel",
         "passthru": null,
@@ -33,11 +53,11 @@
             "name": null,
             "owner": "chipsalliance",
             "repo": "chisel",
-            "rev": "ae5434977a0c0ede55a46847bfcbc8dbf2286c35",
-            "sha256": "sha256-POPpNMnbe4IidbqSlrgBzWHRn6eeL6gh+MuT3v6bw2w=",
+            "rev": "73e96ea5db53ad176e6a9011fc42c888c901d7e2",
+            "sha256": "sha256-VvK0NfvXh4oHn2rj2OWTe1zpONt6ReyvhMGDxa3ikE4=",
             "type": "github"
         },
-        "version": "ae5434977a0c0ede55a46847bfcbc8dbf2286c35"
+        "version": "73e96ea5db53ad176e6a9011fc42c888c901d7e2"
     },
     "chisel-interface": {
         "cargoLocks": null,
@@ -61,7 +81,7 @@
     },
     "riscv-opcodes": {
         "cargoLocks": null,
-        "date": "2024-04-10",
+        "date": "2024-07-24",
         "extract": null,
         "name": "riscv-opcodes",
         "passthru": null,
@@ -73,15 +93,15 @@
             "name": null,
             "owner": "riscv",
             "repo": "riscv-opcodes",
-            "rev": "9fa26954e79d4403eedcbe1b35395001bbbeb8b1",
-            "sha256": "sha256-Gt3v8/VVNhB4IFL7kud8Y7EnSM2/2H4urV1AmBviP9E=",
+            "rev": "07b21cc5143a15959eda12e30aa40cea0971efe0",
+            "sha256": "sha256-B9njfBxZfm7xkSKBD8JOUWIKEzL8ra/X9FKC3CJ2gK8=",
             "type": "github"
         },
-        "version": "9fa26954e79d4403eedcbe1b35395001bbbeb8b1"
+        "version": "07b21cc5143a15959eda12e30aa40cea0971efe0"
     },
     "rvdecoderdb": {
         "cargoLocks": null,
-        "date": "2024-01-28",
+        "date": "2024-07-25",
         "extract": null,
         "name": "rvdecoderdb",
         "passthru": null,
@@ -93,10 +113,10 @@
             "name": null,
             "owner": "sequencer",
             "repo": "rvdecoderdb",
-            "rev": "d65525e7e18004b0877d8fbe2c435296ab986f44",
-            "sha256": "sha256-MzEoFjyUgarR62ux4ngYNFOgvAoeasdr1EVhaCvuh+Q=",
+            "rev": "6f22826d2c8facb6bf0b41f4bea26a2225751220",
+            "sha256": "sha256-4Hwa2Z4mmALy4ZElWzxFgqC+7EsyBhahVYlVUzyYKF4=",
             "type": "github"
         },
-        "version": "d65525e7e18004b0877d8fbe2c435296ab986f44"
-    },
+        "version": "6f22826d2c8facb6bf0b41f4bea26a2225751220"
+    }
 }

nix/t1/_sources/generated.nix

@@ -15,27 +15,27 @@
   };
   berkeley-hardfloat = {
     pname = "berkeley-hardfloat";
-    version = "b3c8a38c286101973b3bc071f7918392343faba7";
+    version = "26f00d00c3f3f57480065e02bfcfde3d3b41ec51";
     src = fetchFromGitHub {
       owner = "ucb-bar";
       repo = "berkeley-hardfloat";
-      rev = "b3c8a38c286101973b3bc071f7918392343faba7";
+      rev = "26f00d00c3f3f57480065e02bfcfde3d3b41ec51";
       fetchSubmodules = false;
-      sha256 = "sha256-3j6K/qFuH8PqJT6zHVTIphq9HWxmSGoIqDo9GV1bxmU=";
+      sha256 = "sha256-gA1Ol7xnzC+10lGwK9+ftfJcMhKsC0KhjENQvUg3u88=";
     };
-    date = "2023-10-25";
+    date = "2024-06-05";
   };
   chisel = {
     pname = "chisel";
-    version = "ae5434977a0c0ede55a46847bfcbc8dbf2286c35";
+    version = "73e96ea5db53ad176e6a9011fc42c888c901d7e2";
     src = fetchFromGitHub {
       owner = "chipsalliance";
       repo = "chisel";
-      rev = "ae5434977a0c0ede55a46847bfcbc8dbf2286c35";
+      rev = "73e96ea5db53ad176e6a9011fc42c888c901d7e2";
       fetchSubmodules = false;
-      sha256 = "sha256-POPpNMnbe4IidbqSlrgBzWHRn6eeL6gh+MuT3v6bw2w=";
+      sha256 = "sha256-VvK0NfvXh4oHn2rj2OWTe1zpONt6ReyvhMGDxa3ikE4=";
     };
-    date = "2024-07-12";
+    date = "2024-07-25";
   };
   chisel-interface = {
     pname = "chisel-interface";
@@ -51,26 +51,26 @@
   };
   riscv-opcodes = {
     pname = "riscv-opcodes";
-    version = "9fa26954e79d4403eedcbe1b35395001bbbeb8b1";
+    version = "07b21cc5143a15959eda12e30aa40cea0971efe0";
     src = fetchFromGitHub {
       owner = "riscv";
       repo = "riscv-opcodes";
-      rev = "9fa26954e79d4403eedcbe1b35395001bbbeb8b1";
+      rev = "07b21cc5143a15959eda12e30aa40cea0971efe0";
       fetchSubmodules = false;
-      sha256 = "sha256-Gt3v8/VVNhB4IFL7kud8Y7EnSM2/2H4urV1AmBviP9E=";
+      sha256 = "sha256-B9njfBxZfm7xkSKBD8JOUWIKEzL8ra/X9FKC3CJ2gK8=";
     };
-    date = "2024-04-10";
+    date = "2024-07-24";
   };
   rvdecoderdb = {
     pname = "rvdecoderdb";
-    version = "d65525e7e18004b0877d8fbe2c435296ab986f44";
+    version = "6f22826d2c8facb6bf0b41f4bea26a2225751220";
     src = fetchFromGitHub {
       owner = "sequencer";
       repo = "rvdecoderdb";
-      rev = "d65525e7e18004b0877d8fbe2c435296ab986f44";
+      rev = "6f22826d2c8facb6bf0b41f4bea26a2225751220";
       fetchSubmodules = false;
-      sha256 = "sha256-MzEoFjyUgarR62ux4ngYNFOgvAoeasdr1EVhaCvuh+Q=";
+      sha256 = "sha256-4Hwa2Z4mmALy4ZElWzxFgqC+7EsyBhahVYlVUzyYKF4=";
     };
-    date = "2024-01-28";
+    date = "2024-07-25";
   };
 }

nix/t1/omreader.nix

@@ -38,7 +38,7 @@ let
           ./../../common.sc
         ];
       };
-      millDepsHash = "sha256-ZwIl6YsaGde3ikbzxLzY2+/XTc5O2dQrOMKcwhKEq+k=";
+      millDepsHash = "sha256-vrxTqskAH7H598ZWRC/+KAXOQlQ6f+gL9c0hvD25xOM=";
       nativeBuildInputs = [ submodules.setupHook ];
     };
 

nix/t1/t1.nix

@@ -41,7 +41,7 @@ let
           ./../../common.sc
         ];
       };
-      millDepsHash = "sha256-ZwIl6YsaGde3ikbzxLzY2+/XTc5O2dQrOMKcwhKEq+k=";
+      millDepsHash = "sha256-vrxTqskAH7H598ZWRC/+KAXOQlQ6f+gL9c0hvD25xOM=";
       nativeBuildInputs = [ submodules.setupHook ];
     };
 

script/build.sc

@@ -10,7 +10,7 @@ trait ScriptModule extends ScalaModule {
   val scala3 = "3.3.3"
   val mainargs = ivy"com.lihaoyi::mainargs:0.5.0"
   val oslib = ivy"com.lihaoyi::os-lib:0.10.0"
-  val upickle = ivy"com.lihaoyi::upickle:3.1.3"
+  val upickle = ivy"com.lihaoyi::upickle:3.3.1"
 
   def scalaVersion = scala3
   def scalacOptions = Seq("-new-syntax")

script/default.nix

@@ -30,7 +30,7 @@ let
               ./build.sc
             ];
           };
-          millDepsHash = "sha256-J8bBgM/F+8x8EQ1DR6Va/ZY2hnsjkkzk4a+ctDMKK3k=";
+          millDepsHash = "sha256-89K7QEq3k50gvs4sbXu7rHajC4tmnQCqB4m5ybBTn6k=";
         };
 
         passthru.withLsp = self.overrideAttrs (old: {

t1/src/Bundles.scala

@@ -10,23 +10,6 @@ import org.chipsalliance.t1.rtl.decoder.Decoder
 import org.chipsalliance.t1.rtl.lsu.LSUParameter
 import org.chipsalliance.t1.rtl.vrf.VRFParam
 
-/** Interface from CPU. */
-class VRequest(xLen: Int) extends Bundle {
-
-  /** instruction fetched by scalar processor. */
-  val instruction: UInt = UInt(32.W)
-
-  /** data read from scalar RF RS1.
-    * TODO: rename to rs1Data
-    */
-  val src1Data: UInt = UInt(xLen.W)
-
-  /** data read from scalar RF RS2.
-    * TODO: rename to rs2Data
-    */
-  val src2Data: UInt = UInt(xLen.W)
-}
-
 /** Interface to CPU. */
 class VResponse(xLen: Int) extends Bundle {
 
@@ -325,9 +308,6 @@ class CSRInterface(vlWidth: Int) extends Bundle {
     * we always keep the undisturbed behavior, since there is no rename here.
     */
   val vma: Bool = Bool()
-
-  /** TODO: remove it. */
-  val ignoreException: Bool = Bool()
 }
 
 /** [[Lane]] -> [[T1]], response for [[LaneRequest]] */
@@ -501,20 +481,11 @@ class VRFWriteReport(param: VRFParam) extends Bundle {
   val state = new VRFInstructionState
 }
 
-/** 为了decode, 指令需要在入口的时候打一拍, 这是需要保存的信息 */
 class InstructionPipeBundle(parameter: T1Parameter) extends Bundle {
-  // 原始指令信息
-  val request: VRequest = new VRequest(parameter.xLen)
-  // decode 的结果
+  val issue: T1Issue = new T1Issue(parameter.xLen, parameter.vLen)
   val decodeResult: DecodeBundle = new DecodeBundle(Decoder.allFields(parameter.decoderParam))
-  // 这条指令被vector分配的index
   val instructionIndex: UInt = UInt(parameter.instructionIndexBits.W)
-  // 指令的csr信息
-  val csr = new CSRInterface(parameter.laneParam.vlMaxBits)
-  // 有写v0的风险
   val vdIsV0: Bool = Bool()
-
-  // How many bytes of registers will be written by one instruction?
   val writeByte: UInt = UInt(parameter.laneParam.vlMaxBits.W)
 }
 
@@ -711,3 +682,44 @@ final class EmptyBundle extends Bundle
 class VRFReadPipe(size: BigInt) extends Bundle {
   val address: UInt = UInt(log2Ceil(size).W)
 }
+
+class T1Issue(xLen: Int, vlWidth: Int) extends Bundle {
+
+  /** instruction fetched by scalar processor. */
+  val instruction: UInt = UInt(32.W)
+
+  /** data read from scalar RF RS1. */
+  val rs1Data: UInt = UInt(xLen.W)
+
+  /** data read from scalar RF RS2. */
+  val rs2Data: UInt = UInt(xLen.W)
+  val vtype: UInt = UInt(32.W)
+  val vl:    UInt = UInt(32.W)
+  val vstart: UInt = UInt(32.W)
+  val vcsr: UInt = UInt(32.W)
+}
+
+object T1Issue {
+  def vlmul(issue: T1Issue) = issue.vtype(2, 0)
+  def vsew(issue: T1Issue) = issue.vtype(5, 3)
+  def vta(issue: T1Issue) = issue.vtype(6)
+  def vma(issue: T1Issue) = issue.vtype(7)
+  def vxrm(issue: T1Issue) = issue.vcsr(2, 1)
+}
+
+class T1RdRetire(xLen: Int) extends Bundle {
+  val rdAddress: UInt = UInt(5.W)
+  val rdData:    UInt = UInt(xLen.W)
+  val isFp:      Bool = Bool()
+}
+
+class T1CSRRetire extends Bundle {
+  val vxsat: UInt = UInt(32.W)
+  val fflag: UInt = UInt(32.W)
+}
+
+class T1Retire(xLen: Int) extends Bundle {
+  val rd:  ValidIO[T1RdRetire] = Valid(new T1RdRetire(xLen))
+  val csr: ValidIO[T1CSRRetire] = Valid(new T1CSRRetire)
+  val mem: ValidIO[EmptyBundle] = Valid(new EmptyBundle)
+}