[t1rocket] use layer api

chipsalliance · Aug 23, 2024 · 7266ae7 · 7266ae7
1 parent 589deb8
commit 7266ae7
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Showing 7 changed files with 67 additions and 55 deletions.
diff --git a/rocketemu/src/TestBench.scala b/rocketemu/src/TestBench.scala
@@ -17,6 +17,7 @@ class TestBench(generator: SerializableModuleGenerator[RocketTile, RocketTilePar
     extends RawModule
     with ImplicitClock
     with ImplicitReset {
+  layer.enable(layers.Verification)
   val clockGen = Module(new ExtModule with HasExtModuleInline {
     override def desiredName = "ClockGen"
     setInline(

diff --git a/rocketv/src/FPU.scala b/rocketv/src/FPU.scala
@@ -46,7 +46,7 @@ class FPUInterface(parameter: FPUParameter) extends Bundle {
   val core = new FPUCoreIO(parameter.hartIdLen, parameter.xLen, parameter.fLen)
   val cp_req = Flipped(Decoupled(new FPInput(parameter.fLen))) //cp doesn't pay attn to kill sigs
   val cp_resp = Decoupled(new FPResult(parameter.fLen))
-  val fpuProbe = Output(Probe(new FPUProbe(parameter)))
+  val fpuProbe = Output(Probe(new FPUProbe(parameter), layers.Verification))
 }
 
 // TODO: all hardfloat module can be replaced by DWBB?
@@ -426,16 +426,19 @@ class FPU(val parameter: FPUParameter)
       wen.orR || divSqrt_inFlight || // post-WB stage
       io.core.dmem_resp_val // load writeback
 
-    // probe defination
-    val probeWire = Wire(new FPUProbe(parameter))
-    define(io.fpuProbe, ProbeValue(probeWire))
+    /* Probes */
+    layer.block(layers.Verification) {
+      val probeWire = Wire(new FPUProbe(parameter))
+      define(io.fpuProbe, ProbeValue(probeWire))
+
+      probeWire.loadOrVectorWrite.rfWen := load_wb
+      probeWire.loadOrVectorWrite.rfWaddr := load_wb_tag
+      probeWire.loadOrVectorWrite.rfWdata := recode(load_wb_data, load_wb_typeTag)
+      probeWire.pipeWrite.rfWen := (!wbInfo(0).cp && wen(0)) || divSqrt_wen
+      probeWire.pipeWrite.rfWaddr := waddr
+      probeWire.pipeWrite.rfWdata := wdata
+    }
 
-    probeWire.loadOrVectorWrite.rfWen := load_wb
-    probeWire.loadOrVectorWrite.rfWaddr := load_wb_tag
-    probeWire.loadOrVectorWrite.rfWdata := recode(load_wb_data, load_wb_typeTag)
-    probeWire.pipeWrite.rfWen := (!wbInfo(0).cp && wen(0)) || divSqrt_wen
-    probeWire.pipeWrite.rfWaddr := waddr
-    probeWire.pipeWrite.rfWdata := wdata
   } // leaving gated-clock domain
   val fpuImpl = withClockAndReset(gated_clock, io.reset) { new FPUImpl }
 }

diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
@@ -349,7 +349,7 @@ class RocketInterface(parameter: RocketParameter) extends Bundle {
   val cease = Output(Bool())
   val wfi = Output(Bool())
   val traceStall = Input(Bool())
-  val rocketProbe = Output(Probe(new RocketProbe(parameter)))
+  val rocketProbe = Output(Probe(new RocketProbe(parameter), layers.Verification))
 }
 
 /** The [[Rocket]] is the next version of the RocketCore,
@@ -438,10 +438,6 @@ class Rocket(val parameter: RocketParameter)
   def minFLen: Int = parameter.minFLen.getOrElse(0)
   def hasDataECC: Boolean = parameter.hasDataECC
 
-  // probe defination
-  val probeWire = Wire(new RocketProbe(parameter))
-  define(io.rocketProbe, ProbeValue(probeWire))
-
   // Signal outside from internal clock domain.
 
   val longLatencyStall = Reg(Bool())
@@ -1093,19 +1089,6 @@ class Rocket(val parameter: RocketParameter)
     )
     when(rfWen) { rf.write(rfWaddr, rfWdata) }
 
-    probeWire.rfWen := rfWen
-    probeWire.rfWaddr := rfWaddr
-    probeWire.rfWdata := rfWdata
-
-    // TODO: add wait enable
-    probeWire.waitWen := wbSetSboard && wbWen
-    probeWire.waitWaddr := wbWaddr
-
-    // FIXME: vectorCSR
-    probeWire.isVector := io.t1.map { t1 =>
-      wbRegDecodeOutput(parameter.decoderParameter.vector) && !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR)
-    }.getOrElse(false.B)
-
     // hook up control/status regfile
     csr.io.ungatedClock := io.clock
     csr.io.decode(0).inst := idInstruction
@@ -1259,21 +1242,7 @@ class Rocket(val parameter: RocketParameter)
             fpScoreboard.clear(dmemResponseReplay && dmemResponseFpu, dmemResponseWaddr)
             t1RetireQueue.foreach(q => fpScoreboard.clear(q.io.deq.fire && q.io.deq.bits.isFp, q.io.deq.bits.rdAddress))
             fpScoreboard.clear(fpu.sboard_clr, fpu.sboard_clra)
-            probeWire.fpuScoreboard.foreach { case fpProbe =>
-              fpProbe.memSetScoreBoard := wbValid && wbDcacheMiss && wbRegDecodeOutput(parameter.decoderParameter.wfd)
-              fpProbe.vectorSetScoreBoard :=wbValid && wbRegDecodeOutput(parameter.decoderParameter.wfd) && Option.when(usingVector)(wbRegDecodeOutput(parameter.decoderParameter.vector)).getOrElse(false.B)
-              fpProbe.fpuSetScoreBoard := wbValid && wbRegDecodeOutput(parameter.decoderParameter.wfd) && fpu.sboard_set
-              fpProbe.scoreBoardSetAddress := wbWaddr
 
-              fpProbe.fpuClearScoreBoard.valid := fpu.sboard_clr
-              fpProbe.fpuClearScoreBoard.bits := fpu.sboard_clra
-
-              fpProbe.vectorClearScoreBoard.valid := t1RetireQueue.map(q => q.io.deq.fire && q.io.deq.bits.isFp).getOrElse(false.B)
-              fpProbe.vectorClearScoreBoard.bits := t1RetireQueue.map(q => q.io.deq.bits.rdAddress).getOrElse(0.U)
-
-              fpProbe.memClearScoreBoard.valid := dmemResponseReplay && dmemResponseFpu
-              fpProbe.memClearScoreBoard.bits := dmemResponseWaddr
-            }
             checkHazards(fpHazardTargets, fpScoreboard.read)
         }
         .getOrElse(false.B)
@@ -1457,7 +1426,6 @@ class Rocket(val parameter: RocketParameter)
       val (vectorEmpty, vectorFull) = counterManagement(countWidth, 4)(t1IssueQueue.io.enq.valid, t1.issue.fire)
       vectorLSUEmpty.foreach(_ := lsuEmpty)
       vectorQueueFull.foreach(_ := vectorFull)
-      probeWire.idle := vectorEmpty
 
       t1XRDRetireQueue.io.enq.valid := t1.retire.rd.valid
       t1XRDRetireQueue.io.enq.bits := t1.retire.rd.bits
@@ -1484,6 +1452,42 @@ class Rocket(val parameter: RocketParameter)
           fpu.dmem_resp_tag := t1XRDRetireQueue.io.deq.bits.rdAddress
         }
       }
+
+      // probe defination
+      layer.block(layers.Verification) {
+        val probeWire = Wire(new RocketProbe(parameter))
+        define(io.rocketProbe, ProbeValue(probeWire))
+
+        probeWire.rfWen := rfWen
+        probeWire.rfWaddr := rfWaddr
+        probeWire.rfWdata := rfWdata
+
+        probeWire.waitWen := wbSetSboard && wbWen
+        probeWire.waitWaddr := wbWaddr
+        // FIXME: vectorCSR
+        probeWire.isVector := io.t1.map { t1 =>
+          wbRegDecodeOutput(parameter.decoderParameter.vector) && !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR)
+        }.getOrElse(false.B)
+        probeWire.idle := vectorEmpty
+
+        probeWire.fpuScoreboard.foreach { case fpProbe =>
+          fpProbe.memSetScoreBoard := wbValid && wbDcacheMiss && wbRegDecodeOutput(parameter.decoderParameter.wfd)
+          fpProbe.vectorSetScoreBoard := wbValid && wbRegDecodeOutput(parameter.decoderParameter.wfd) && Option.when(usingVector)(wbRegDecodeOutput(parameter.decoderParameter.vector)).getOrElse(false.B)
+          fpProbe.scoreBoardSetAddress := wbWaddr
+
+          io.fpu.map { fpu =>
+            fpProbe.fpuSetScoreBoard := wbValid && wbRegDecodeOutput(parameter.decoderParameter.wfd) && fpu.sboard_set
+            fpProbe.fpuClearScoreBoard.valid := fpu.sboard_clr
+            fpProbe.fpuClearScoreBoard.bits := fpu.sboard_clra
+          }
+
+          fpProbe.vectorClearScoreBoard.valid := t1RetireQueue.map(q => q.io.deq.fire && q.io.deq.bits.isFp).getOrElse(false.B)
+          fpProbe.vectorClearScoreBoard.bits := t1RetireQueue.map(q => q.io.deq.bits.rdAddress).getOrElse(0.U)
+
+          fpProbe.memClearScoreBoard.valid := dmemResponseReplay && dmemResponseFpu
+          fpProbe.memClearScoreBoard.bits := dmemResponseWaddr
+        }
+      }
     }
 
     io.dmem.req.valid := exRegValid && exRegDecodeOutput(parameter.decoderParameter.mem)
@@ -1572,7 +1576,6 @@ class Rocket(val parameter: RocketParameter)
       when(ens) { _r := _next }
     }
   }
-
 }
 
 class RegFile(n: Int, w: Int, zero: Boolean = false) {

diff --git a/rocketv/src/RocketTile.scala b/rocketv/src/RocketTile.scala
@@ -396,7 +396,7 @@ class RocketTileInterface(parameter: RocketTileParameter) extends Bundle {
   val dtimAXI: Option[AXI4RWIrrevocable] =
     parameter.dtimParameter.map(p => Flipped(org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(p)))
 
-  val rocketProbe = Output(Probe(new RocketProbe(parameter.rocketParameter)))
+  val rocketProbe = Output(Probe(new RocketProbe(parameter.rocketParameter), layers.Verification))
 }
 
 class RocketTile(val parameter: RocketTileParameter)
@@ -478,6 +478,8 @@ class RocketTile(val parameter: RocketTileParameter)
     fpu.io.cp_resp <> DontCare
   }
 
-  // probe
-  define(io.rocketProbe, rocket.io.rocketProbe)
+  /* Probes */
+  layer.block(layers.Verification) {
+    define(io.rocketProbe, rocket.io.rocketProbe)
+  }
 }
diff --git a/t1/src/lsu/LoadUnit.scala b/t1/src/lsu/LoadUnit.scala
@@ -311,7 +311,7 @@ class LoadUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
     val probe = IO(Output(Probe(Bool(), layers.Verification)))
     layer.block(layers.Verification) {
       define(probe, ProbeValue(port.ready))
-      }
+    }
     probe
   }).toSeq
 

diff --git a/t1rocket/src/T1RocketTile.scala b/t1rocket/src/T1RocketTile.scala
@@ -465,7 +465,7 @@ class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle {
   val highOutstandingAXI: AXI4RWIrrevocable = org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(parameter.t1HightOutstandingParameter)
 
   // TODO: merge it.
-  val t1RocketProbe: T1RocketProbe = Output(Probe(new T1RocketProbe(parameter)))
+  val t1RocketProbe: T1RocketProbe = Output(Probe(new T1RocketProbe(parameter), layers.Verification))
 }
 
 class T1RocketTile(val parameter: T1RocketTileParameter)
@@ -560,11 +560,13 @@ class T1RocketTile(val parameter: T1RocketTileParameter)
   io.highOutstandingAXI <> t1.io.indexedLoadStorePort
 
   // probe
-  val probeWire = Wire(new T1RocketProbe(parameter))
-  define(io.t1RocketProbe, ProbeValue(probeWire))
-  probeWire.rocketProbe := probe.read(rocket.io.rocketProbe)
-  probeWire.t1Probe := probe.read(t1.io.t1Probe)
-  probeWire.fpuProbe.foreach { fpuProbe =>
-    fpuProbe := probe.read(fpu.get.io.fpuProbe)
+  layer.block(layers.Verification) {
+    val probeWire = Wire(new T1RocketProbe(parameter))
+    define(io.t1RocketProbe, ProbeValue(probeWire))
+    probeWire.rocketProbe := probe.read(rocket.io.rocketProbe)
+    probeWire.t1Probe := probe.read(t1.io.t1Probe)
+    probeWire.fpuProbe.foreach { fpuProbe =>
+      fpuProbe := probe.read(fpu.get.io.fpuProbe)
+    }
   }
 }
diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
@@ -18,6 +18,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
     extends RawModule
     with ImplicitClock
     with ImplicitReset {
+  layer.enable(layers.Verification)
   val clockGen = Module(new ExtModule with HasExtModuleInline {
     override def desiredName = "ClockGen"
     setInline(