[difftest] fix test bench.

chipsalliance · Jul 8, 2024 · 7e0a6df · 7e0a6df
1 parent 1d12f83
commit 7e0a6df
Showing 1 changed file with 12 additions and 12 deletions.
diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala
@@ -6,7 +6,7 @@ package org.chipsalliance.t1.ipemu
 import chisel3._
 import chisel3.experimental.SerializableModuleGenerator
 import chisel3.experimental.dataview.DataViewable
-import chisel3.util.{Valid, log2Ceil}
+import chisel3.util.{UIntToOH, Valid, log2Ceil}
 import chisel3.util.circt.dpi.{RawClockedNonVoidFunctionCall, RawClockedVoidFunctionCall, RawUnlockedNonVoidFunctionCall}
 import org.chipsalliance.amba.axi4.bundle._
 import org.chipsalliance.t1.ipemu.dpi._
@@ -167,13 +167,12 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
     when(lsuProbe.reqEnq.orR)(printf(cf"""{"event":"LsuEnq","enq":${lsuProbe.reqEnq},"cycle": ${simulationTime}}\n"""))
 
     // allocate 2 * chainingSize scoreboards
-    val vrfWriteScoreboard = Seq.tabulate(2 * dut.parameter.chainingSize) { _ => RegInit(0.U.asTypeOf(Valid(UInt(16.W))))}
-    when(dut.request.fire) {
-      val scoreboard: Valid[UInt] = VecInit(vrfWriteScoreboard)(t1Probe.instructionCounter)
-      scoreboard.valid := true.B
-      assert(!scoreboard.valid)
-      scoreboard.bits := 0.U
-    }
+    val vrfWriteScoreboard: Seq[Valid[UInt]] = Seq.tabulate(2 * dut.parameter.chainingSize) { _ => RegInit(0.U.asTypeOf(Valid(UInt(16.W))))}
+    vrfWriteScoreboard.foreach(scoreboard => dontTouch(scoreboard))
+    val instructionValid =
+      (laneProbes.map(laneProbe => laneProbe.instructionValid) :+
+        lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _)
+    val scoreboardEnq = Mux(dut.request.fire, UIntToOH(t1Probe.instructionCounter), 0.U((2 * dut.parameter.chainingSize).W))
     vrfWriteScoreboard.zipWithIndex.foreach { case (scoreboard, tag) =>
       // always equal to array index
       scoreboard.bits :=
@@ -185,15 +184,16 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
             // vrf write from Sequencer
             Some(t1Probe.writeQueueEnq.bits === tag.U && t1Probe.writeQueueEnq.valid)
           ).reduce[UInt](_ + _)
-
-      val instructionValid =
-        (laneProbes.map(laneProbe => laneProbe.instructionValid) :+
-          lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _)
       val tagTruncation: Int = (1 << log2Ceil(dut.parameter.chainingSize)) - 1
       when(scoreboard.valid && !instructionValid(tag & tagTruncation)){
         printf(cf"""{"event":"VrfScoreboardReport","count":${scoreboard.bits},"tag":${tag},"cycle": ${simulationTime}}\n""")
         scoreboard.valid := false.B
       }
+      when(scoreboardEnq(tag)) {
+        scoreboard.valid := true.B
+        assert(!scoreboard.valid)
+        scoreboard.bits := 0.U
+      }
     }
   }
 }