[rtl] fix logic.

chipsalliance · Dec 12, 2024 · 889f7b1 · 889f7b1
1 parent bdcb66e
commit 889f7b1
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/t1/src/LaneLogic.scala b/t1/src/LaneLogic.scala
@@ -46,7 +46,7 @@ class LaneLogic(val parameter: LaneLogicParameter)
   resp := VecInit(req.src.map(_.asBools).transpose.map { case Seq(sr0, sr1) =>
     chisel3.util.experimental.decode.decoder
       .qmc(
-        req.opcode ## (sr0 ## (req.opcode(2) ^ sr1)),
+        req.opcode(1, 0) ## (sr0 ## (req.opcode(2) ^ sr1)),
         TruthTable(TableGenerator.LogicTable.table, BitPat.dontCare(1))
       ) ^
       req.opcode(3)

diff --git a/t1/src/MaskedLogic.scala b/t1/src/MaskedLogic.scala
@@ -55,7 +55,7 @@ class MaskedLogic(val parameter: LogicParam) extends VFUModule with Serializable
       sr3,
       chisel3.util.experimental.decode.decoder
         .qmc(
-          request.opcode ## ((request.opcode(2) ^ sr0) ## sr1),
+          request.opcode(1, 0) ## ((request.opcode(2) ^ sr0) ## sr1),
           TruthTable(TableGenerator.LogicTable.table, BitPat.dontCare(1))
         ) ^ request.opcode(3),
       sr2