[difftest] fix vrfWriteScoreboard update.

chipsalliance · Jul 10, 2024 · ac9db6b · ac9db6b
1 parent 1b10617
commit ac9db6b
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Showing 3 changed files with 22 additions and 14 deletions.
diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala
@@ -6,7 +6,7 @@ package org.chipsalliance.t1.ipemu
 import chisel3._
 import chisel3.experimental.SerializableModuleGenerator
 import chisel3.experimental.dataview.DataViewable
-import chisel3.util.{UIntToOH, Valid, log2Ceil}
+import chisel3.util.{PopCount, UIntToOH, Valid, log2Ceil}
 import chisel3.util.circt.dpi.{RawClockedNonVoidFunctionCall, RawClockedVoidFunctionCall, RawUnlockedNonVoidFunctionCall}
 import org.chipsalliance.amba.axi4.bundle._
 import org.chipsalliance.t1.ipemu.dpi._
@@ -172,18 +172,20 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
     val instructionValid =
       (laneProbes.map(laneProbe => laneProbe.instructionValid) :+
         lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _)
-    val scoreboardEnq = Mux(dut.request.fire, UIntToOH(t1Probe.instructionCounter), 0.U((2 * dut.parameter.chainingSize).W))
+    val scoreboardEnq = Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * dut.parameter.chainingSize).W))
     vrfWriteScoreboard.zipWithIndex.foreach { case (scoreboard, tag) =>
+      val writeEnq: UInt = VecInit(
+        // vrf write from lane
+        laneProbes.flatMap(laneProbe => laneProbe.slots.map(slot =>
+          slot.writeTag === tag.U && slot.writeQueueEnq && slot.writeMask.orR
+        )) ++
+          // vrf write from lsu
+          lsuProbe.slots.map(slot => slot.dataInstruction === tag.U && slot.writeValid && slot.dataMask.orR) ++
+          // vrf write from Sequencer
+          Some(t1Probe.writeQueueEnq.bits === tag.U && t1Probe.writeQueueEnq.valid && t1Probe.writeQueueEnqMask.orR)
+        ).asUInt
       // always equal to array index
-      scoreboard.bits :=
-        (
-          // vrf write from lane
-          laneProbes.flatMap(laneProbe => laneProbe.slots.map(slot => slot.writeTag === tag.U && slot.writeQueueEnq)) ++
-            // vrf write from lsu
-            lsuProbe.slots.map(slot => slot.dataInstruction === tag.U && slot.writeValid) ++
-            // vrf write from Sequencer
-            Some(t1Probe.writeQueueEnq.bits === tag.U && t1Probe.writeQueueEnq.valid)
-          ).reduce[UInt](_ + _)
+      scoreboard.bits := scoreboard.bits + PopCount(writeEnq)
       val tagTruncation: Int = (1 << log2Ceil(dut.parameter.chainingSize)) - 1
       when(scoreboard.valid && !instructionValid(tag & tagTruncation)){
         printf(cf"""{"event":"VrfScoreboardReport","count":${scoreboard.bits},"tag":${tag},"cycle":${simulationTime}}\n""")

diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -45,6 +45,7 @@ class LaneSlotProbe(instructionIndexBit: Int) extends Bundle {
   // write queue enq for lane
   val writeQueueEnq: Bool = Bool()
   val writeTag: UInt = UInt(instructionIndexBit.W)
+  val writeMask: UInt = UInt(4.W)
 }
 
 class LaneProbe(slotsSize: Int, instructionIndexBit: Int) extends Bundle {
@@ -815,6 +816,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
       probeWire.slots(index).stage3VrfWriteValid := stage3.vrfWriteRequest.valid
       probeWire.slots(index).writeQueueEnq := stage3.vrfWriteRequest.fire
       probeWire.slots(index).writeTag := stage3.vrfWriteRequest.bits.instructionIndex
+      probeWire.slots(index).writeMask := stage3.vrfWriteRequest.bits.mask
       // probeWire.slots(index).probeStage1 := ???
   }
 

diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -272,8 +272,11 @@ case class T1Parameter(
 
 class T1Probe(param: T1Parameter) extends Bundle {
   val instructionCounter: UInt = UInt(param.instructionIndexBits.W)
+  val instructionIssue: Bool = Bool()
+  val issueTag: UInt = UInt(param.instructionIndexBits.W)
   // write queue enq for mask unit
   val writeQueueEnq: ValidIO[UInt] = Valid(UInt(param.instructionIndexBits.W))
+  val writeQueueEnqMask: UInt = UInt((param.datapathWidth / 8).W)
   // mask unit instruction valid
   val instructionValid: UInt = UInt(param.chainingSize.W)
 }
@@ -1688,14 +1691,15 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
   val probeWire = Wire(new T1Probe(parameter))
   define(t1Probe, ProbeValue(probeWire))
   probeWire.instructionCounter := instructionCounter
+  probeWire.instructionIssue := requestRegDequeue.fire
+  probeWire.issueTag := requestReg.bits.instructionIndex
   // maskUnitWrite maskUnitWriteReady
   probeWire.writeQueueEnq.valid := maskUnitWrite.valid && maskUnitWriteReady
   probeWire.writeQueueEnq.bits := maskUnitWrite.bits.instructionIndex
+  probeWire.writeQueueEnqMask := maskUnitWrite.bits.mask
   probeWire.instructionValid := maskAnd(
     !slots.last.state.sMaskUnitExecution && !slots.last.state.idle,
-    indexToOH(slots.last.record.instructionIndex, parameter.chainingSize)).asUInt |
-    // instruction in requestReg
-    maskAnd(requestReg.valid, indexToOH(requestReg.bits.instructionIndex, parameter.chainingSize)).asUInt
+    indexToOH(slots.last.record.instructionIndex, parameter.chainingSize)).asUInt
 
 
   // new V Request from core