[rtl] fix connect for simpleAccessPorts.aw

chipsalliance · Jul 17, 2024 · cff1cbe · cff1cbe
1 parent 3893c36
commit cff1cbe
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala
@@ -404,7 +404,7 @@ class LSU(param: LSUParameter) extends Module {
   simpleSourceQueue.io.deq.ready := simpleAccessPorts.r.fire
 
   val simpleDataQueue: Queue[SimpleMemWrite] = Module(new Queue(chiselTypeOf(otherUnit.memWriteRequest.bits), 2))
-  simpleAccessPorts.aw.valid := storeUnit.memRequest.valid && dataQueue.io.enq.ready
+  simpleAccessPorts.aw.valid := otherUnit.memWriteRequest.valid && dataQueue.io.enq.ready
   simpleAccessPorts.aw.bits <> DontCare
   simpleAccessPorts.aw.bits.len := 0.U
   simpleAccessPorts.aw.bits.burst := 1.U //INCR