Errors occur when modify axpy-masked.mlir in some ways

[xlinsist]

In the buddy case axpy-masked.mlir(AX plus Y cases with mask operations), errors will occur if we modify it in the following way:

1. Changing %mask64 = arith.constant dense<1> : vector<64xi1> to %mask64 = vector.create_mask %remain : vector<64xi1>, which means using another way to define variable mask64. It will lead to spike trapped with trap_illegal_instruction error.

2. Replacing all the number "64" with number "128", which means extending the number of elements processed at the same time. In that case the following error message will be shown:

...
I20230602 01:54:01.164361 56366 vbridge_impl.cc:118] [539776] poke instruction (pc=000114E0, bits=02830427, disasm='vs1r.v  v8, (t1)', rs1=00010DDC, rs2=00000000)
I20230602 01:54:01.164507 56366 vbridge_impl.cc:330] [539777] <- receive rtl mem put req (addr=00010E5C, size=4byte, src=0000, data=0)
E20230602 01:54:01.164541 56366 vbridge_impl.cc:358] Check failed: actual_data == data (4294967295 vs. 0) : [539777] expect mem write of data FFFFFFFF, actual data 00000000 (addr=00010E5F, insn='pc=000114B0, bits=02830427, disasm='vs1r.v  v8, (t1)'')
E20230602 01:54:01.164623 56366 dpi.cc:116] detect exception (check failed), gracefully abort simulation
1 targets failed
tests.run[axpy-masked.mlir].run os.SubprocessException: CommandResult 134
[539777] %Error: verbatim.sv:33: Assertion failed in TOP.TestBench.verificationModule.verbatim.dpiError: check failed

[xlinsist]

After testing based on the latest repository, the two errors mentioned above still exist and present messages in the following way:

1. Changing %mask64 = arith.constant dense<1> : vector<64xi1> to %mask64 = vector.create_mask %remain : vector<64xi1> will lead to

I20230627 01:39:00.614322 74916 vbridge_impl.cc:89] [501876] rtl commit insn (pc=000113EC, bits=5E00B557, disasm='vmv.v.i v10, 1')
I20230627 01:39:00.614332 74916 vbridge_impl.cc:118] [501876] poke instruction (pc=000113F8, bits=42802557, disasm='vmv.x.s a0, v8', rs1=00000000, rs2=00000000)
I20230627 01:39:00.614547 74916 vbridge_impl.cc:134] [501877] issue to rtl (pc=000113F8, bits=42802557, disasm='vmv.x.s a0, v8', issue_idx=2)
I20230627 01:39:00.615702 74916 vbridge_impl.cc:223] spike run (pc=000113FC, bits=C22025F3, disasm=csrr    a1, vlenb)
I20230627 01:39:00.615754 74916 vbridge_impl.cc:223] spike run (pc=000113FC, bits=C22025F3, disasm=csrr    a1, vlenb)
I20230627 01:39:00.615768 74916 vbridge_impl.cc:223] spike run (pc=00011400, bits=00459593, disasm=slli    a1, a1, 4)
I20230627 01:39:00.615782 74916 vbridge_impl.cc:223] spike run (pc=00011404, bits=00B10133, disasm=add     sp, sp, a1)
I20230627 01:39:00.615794 74916 vbridge_impl.cc:223] spike run (pc=00011408, bits=01010113, disasm=addi    sp, sp, 16)
I20230627 01:39:00.615804 74916 vbridge_impl.cc:223] spike run (pc=0001140C, bits=00008067, disasm=ret)
I20230627 01:39:00.615816 74916 vbridge_impl.cc:223] spike run (pc=000111D8, bits=00000000, disasm=c.unimp)
E20230627 01:39:00.615880 74916 vbridge_impl.cc:472] spike trapped with trap_illegal_instruction
E20230627 01:39:00.615901 74916 dpi.cc:94] detect exception (check failed), gracefully abort simulation
1 targets failed
tests.run[axpy-masked.mlir].run os.SubprocessException: CommandResult 134
[501886] %Error: verbatim.sv:33: Assertion failed in TOP.TestBench.verificationModule.verbatim.dpiError: check failed
%Error: /home/xlinsist/RVV/vector/out/tests/mfccompile/compile.dest/verbatim.sv:33: Verilog $stop
Aborting...

The message doesn't explictly show which assembly instructions don't work on spike. Does it suggest that we should avoid using vector.create_mask when writing mlir cases? @sequencer

---

2. Replacing all the number "64" with number "128" will present the following message:

...
I20230625 09:18:53.556495 56794 vbridge_impl.cc:387] [691767] -> tl response reaches d_ready (channel=0 addr=000A8E2D)
I20230625 09:18:53.557355 56794 vbridge_impl.cc:118] [691776] poke instruction (pc=00011448, bits=E2830827, disasm='vs8r.v  v16, (t1)', rs1=00010EDC, rs2=00000000)
I20230625 09:18:53.557384 56794 vbridge_impl.cc:440] [691776] waiting for lsu request to fire.
I20230625 09:18:53.557507 56794 vbridge_impl.cc:134] [691777] issue to rtl (pc=00011448, bits=E2830827, disasm='vs8r.v  v16, (t1)', issue_idx=2)
1 targets failed
tests.run[axpy-masked.mlir].run os.SubprocessException: CommandResult 134
[691785] %Error: Lane.sv:5438: Assertion failed in TOP.TestBench.dut.laneVec_0: Assertion failed
    at Lane.scala:1548 assert(laneResponseFeedback.bits.instructionIndex === record.laneRequest.instructionIndex)

%Error: /home/xlinsist/RVV/vector/out/tests/mfccompile/compile.dest/Lane.sv:5438: Verilog $stop
Aborting...

This error is somewhat puzzling to me.