pipe vrf access

t1/src/Bundles.scala

@@ -692,3 +692,13 @@ class VFUResponseToSlot(parameter: LaneParameter) extends Bundle {
 }
 
 final class EmptyBundle extends Bundle
+
+
+class VRFReadPipe(size: BigInt) extends Bundle {
+  val address: UInt = UInt(log2Ceil(size).W)
+}
+
+class DataPipeInReadStage(dataWidth: Int, arbitrate: Boolean) extends Bundle {
+  val data: UInt = UInt(dataWidth.W)
+  val choose: Option[Bool] = Option.when(arbitrate)(Bool())
+}

t1/src/Lane.scala

@@ -1045,7 +1045,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   laneRequest.ready := !slotOccupied.last && vrf.instructionWriteReport.ready
 
   val instructionFinishAndNotReportByTop: Bool =
-    entranceControl.instructionFinished && !laneRequest.bits.decodeResult(Decoder.readOnly)
+    entranceControl.instructionFinished && !laneRequest.bits.decodeResult(Decoder.readOnly) && (writeCount === 0.U)
   val needWaitCrossWrite: Bool = laneRequest.bits.decodeResult(Decoder.crossWrite) && csrInterface.vl.orR
   // normal instruction, LSU instruction will be report to VRF.
   vrf.instructionWriteReport.valid := laneRequest.bits.issueInst && (!instructionFinishAndNotReportByTop || needWaitCrossWrite)
@@ -1113,7 +1113,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
       Mux(topWriteQueue.valid, indexToOH(topWriteQueue.bits.instructionIndex, parameter.chainingSize), 0.U) |
       maskedWriteUnit.maskedWrite1H | dataInPipeQueue
   instructionFinished := instructionFinishedVec.reduce(_ | _)
-  crossWriteDataInSlot := crossWriteDataInSlotVec.reduce(_ | _)
+  crossWriteDataInSlot := crossWriteDataInSlotVec.reduce(_ | _) | dataInPipeQueue | maskedWriteUnit.maskedWrite1H
   writeReadyForLsu := vrf.writeReadyForLsu
   vrfReadyToStore := vrf.vrfReadyToStore
 

t1/src/T1.scala

@@ -9,9 +9,7 @@ import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.util._
 import chisel3.util.experimental.decode._
 import tilelink.{TLBundle, TLBundleParameter, TLChannelAParameter, TLChannelDParameter}
-import chisel3.probe.Probe
-import chisel3.probe.ProbeValue
-import chisel3.probe.define
+import chisel3.probe.{Probe, ProbeValue, define, force}
 import chisel3.util.experimental.BitSet
 import org.chipsalliance.t1.rtl.decoder.Decoder
 import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe}
@@ -181,7 +179,7 @@ case class T1Parameter(
   val maskWidth: Int = lsuBankParameters.head.beatbyte
 
   // todo
-  val vrfReadLatency = 1
+  val vrfReadLatency = 2
 
   // each element: Each lane will be connected to the other two lanes,
   // and the values are their respective delays.
@@ -480,7 +478,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
     RegEnable(
       !requestRegDequeue.fire,
       false.B,
-      (RegNext(maskUnitReadReady) && gatherNeedRead) || requestRegDequeue.fire
+      (RegNext(RegNext(maskUnitReadReady)) && gatherNeedRead) || requestRegDequeue.fire
     )
   val gatherReadDataOffset: UInt = Wire(UInt(5.W))
   val gatherData:           UInt = Mux(gatherOverlap, 0.U, (WARRedResult.bits >> gatherReadDataOffset).asUInt)
@@ -760,7 +758,8 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
       val lastExecuteForGroup = writeBackCounter.andR
       // 计算正写的这个lane是不是在边界上
       val endOH = UIntToOH(csrRegForMaskUnit.vl(parameter.dataPathWidthBits - 1, 0))
-      val border = lastExecute && dataPathMisaligned && !(decodeResultReg(Decoder.compress))
+      val border = lastExecute && dataPathMisaligned &&
+        !(decodeResultReg(Decoder.compress) || decodeResultReg(Decoder.gather))
       val lastGroupMask = scanRightOr(endOH(parameter.datapathWidth - 1, 1))
       val mvType = decodeResultReg(Decoder.mv)
       val readMv = mvType && decodeResultReg(Decoder.targetRd)
@@ -772,13 +771,17 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
       val skipLaneData: Bool = decodeResultReg(Decoder.mv)
       mixedUnit := writeMv || readMv
       maskReadLaneSelect.head := UIntToOH(writeBackCounter)
+      maskReadLaneSelect.head := UIntToOH(writeBackCounter)
       maskWriteLaneSelect.head := maskReadLaneSelect.head
       maskUnitReadVec.head.valid := false.B
       maskUnitReadVec.head.bits.vs := Mux(readMv, vs2, Mux(reduce, vs1, vd))
       maskUnitReadVec.head.bits.readSource := Mux(readMv, 1.U, Mux(reduce, 0.U, 2.U))
       maskUnitReadVec.head.bits.offset := groupCounter
       maskUnitRead.bits.instructionIndex := control.record.instructionIndex
-      val readResultSelectResult = Mux1H(RegNext(maskUnitReadSelect), laneReadResult)
+      val readResultSelectResult = Mux1H(
+        Pipe(true.B, maskUnitReadSelect, parameter.vrfReadLatency).bits
+        , laneReadResult
+      )
       // 把mask选出来
       val maskSelect = v0(groupCounter ## writeBackCounter)
       val fullMask: UInt = (-1.S(parameter.datapathWidth.W)).asUInt
@@ -802,8 +805,11 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
       maskUnitWriteVec.head.bits.last := control.state.wLast || reduce
       maskUnitWriteVec.head.bits.instructionIndex := control.record.instructionIndex
 
-      val maskUnitReadVrf = maskUnitReadReady && maskUnitReadVec.map(_.valid).reduce(_ || _)
-      when(RegNext(maskUnitReadVrf)) {
+      val waitReadResult: Bool = Wire(Bool())
+      val maskUnitReadVrf = maskUnitReadReady && maskUnitReadVec.map(_.valid).reduce(_ || _) && !waitReadResult
+      val readNext = RegNext(maskUnitReadVrf)
+      waitReadResult := RegNext(readNext) || readNext
+      when(Pipe(maskUnitReadVrf, false.B, parameter.vrfReadLatency).valid) {
         WARRedResult.bits := readResultSelectResult
         WARRedResult.valid := true.B
       }
@@ -993,8 +999,10 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
       val skipRead = readOverlap || (gather && compareResult) || extend
       val maskUnitWriteVecFire1 = maskUnitReadVec(1).valid && maskUnitReadReady
       val readFireNext1: Bool = RegNext(maskUnitWriteVecFire1)
-      val gatherTryToRead = gatherNeedRead && !VecInit(lsu.vrfReadDataPorts.map(_.valid)).asUInt.orR
-      maskUnitReadVec(1).valid := (readState || gatherTryToRead) && !readFireNext1
+      val readFireNextNext1: Bool = RegNext(readFireNext1)
+      val port1WaitForResult: Bool = readFireNext1 || readFireNextNext1
+      val gatherTryToRead = gatherNeedRead && !VecInit(lsu.vrfReadDataPorts.map(_.valid)).asUInt.orR && !gatherReadFinish
+      maskUnitReadVec(1).valid := (readState || gatherTryToRead) && !port1WaitForResult
       maskUnitReadVec(1).bits.vs := Mux(readState, vs2, requestRegDequeue.bits.instruction(24, 20)) + readGrowth
       maskUnitReadVec(1).bits.readSource := 1.U
       maskUnitReadVec(1).bits.offset := readOffset
@@ -1044,7 +1052,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
       }
       when(readState) {
         // 不需要valid,因为这个状态下一定是valid的
-        when(readFireNext1) {
+        when(readFireNextNext1) {
           slideState := sWrite
         }
       }
@@ -1080,7 +1088,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
       val compressStateWrite = compressState === sWrite1
 
       // compress 用vs1当mask,需要先读vs1
-      val readCompressMaskNext = RegNext(maskUnitReadReady && compressStateRead)
+      val readCompressMaskNext = Pipe(maskUnitReadReady && compressStateRead, false.B, parameter.vrfReadLatency).valid
       when(readCompressMaskNext) {
         maskDataForCompress := readResultSelectResult
       }
@@ -1093,6 +1101,8 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
 
       val maskUnitReadFire2: Bool = maskUnitReadVec(2).valid && maskUnitReadReady
       val readFireNext2 = RegNext(maskUnitReadFire2)
+      val readFireNextNext2 = RegNext(readFireNext2)
+      val port2WaitForResult = readFireNextNext2 || readFireNext2
 
       /** 计算需要读的mask的相关
         * elementIndexCount -> 11bit
@@ -1102,7 +1112,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
         * elementIndexCount(9, 8)作为offset
         */
       // compress read
-      maskUnitReadVec(2).valid := compressStateRead && !readFireNext2
+      maskUnitReadVec(2).valid := compressStateRead && !port2WaitForResult
       maskUnitReadVec(2).bits.vs := vs1
       maskUnitReadVec(2).bits.readSource := 0.U
       maskUnitReadVec(2).bits.offset := elementIndexCount(
@@ -1143,7 +1153,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
         compressState := firstState
       }
 
-      when(compressStateRead && readFireNext2) {
+      when(compressStateRead && readFireNextNext2) {
         compressState := sWrite1
       }
 

t1/src/laneStage/LaneStage1.scala

@@ -103,9 +103,9 @@ class LaneStage1(parameter: LaneParameter, isLastSlot: Boolean) extends Module {
   enqueue.ready := allReadQueueReady && pipeQueue.io.enq.ready
 
   // request enqueue
-  readRequestQueueVs1.io.enq.valid := enqueue.valid && allReadQueueReady && state.decodeResult(Decoder.vtype) && !state.skipRead
-  readRequestQueueVs2.io.enq.valid := enqueue.valid && allReadQueueReady && !state.skipRead
-  readRequestQueueVd.io.enq.valid := enqueue.valid && allReadQueueReady && !state.decodeResult(Decoder.sReadVD)
+  readRequestQueueVs1.io.enq.valid := enqueue.fire && state.decodeResult(Decoder.vtype) && !state.skipRead
+  readRequestQueueVs2.io.enq.valid := enqueue.fire && !state.skipRead
+  readRequestQueueVd.io.enq.valid := enqueue.fire && !state.decodeResult(Decoder.sReadVD)
   (readRequestQueueLSB ++ readRequestQueueMSB).foreach { q =>
     q.io.enq.valid := enqueue.valid && allReadQueueReady && state.decodeResult(Decoder.crossRead)
   }

t1/src/laneStage/MaskedWrite.scala

@@ -6,8 +6,17 @@ package org.chipsalliance.t1.rtl.lane
 import chisel3._
 import chisel3.experimental.hierarchy.{instantiable, public}
 import chisel3.util._
-import org.chipsalliance.t1.rtl.{LaneParameter, VRFReadRequest, VRFWriteRequest, ffo, indexToOH}
+import org.chipsalliance.t1.rtl.{LaneParameter, VRFReadRequest, VRFWriteRequest, ffo, indexToOH, maskAnd}
 
+import scala.annotation.unused
+
+/** s0 enqueue read fire
+ * raw check: hit s1, hit s2, hit s3
+ *
+ * s1 wait arbiter(reg)
+ * s2 wait sram read(reg)
+ * s3 dequeu(reg)
+ **/
 @instantiable
 class MaskedWrite(parameter: LaneParameter) extends Module {
   val vrfWriteBundle: VRFWriteRequest = new VRFWriteRequest(
@@ -31,40 +40,117 @@ class MaskedWrite(parameter: LaneParameter) extends Module {
    */
   @public
   val vrfReadResult: UInt = IO(Input(UInt(parameter.datapathWidth.W)))
+
+  def address(req: VRFWriteRequest): UInt = req.vd ## req.offset
+
+  val dequeueWire: DecoupledIO[VRFWriteRequest] = Wire(chiselTypeOf(dequeue))
+  val dequeueQueue: Queue[VRFWriteRequest] = Module(new Queue(chiselTypeOf(dequeue.bits), 1, flow = true))
+  dequeueQueue.io.enq <> dequeueWire
+  val s3Valid: Bool = RegInit(false.B)
+  val s3Pipe: VRFWriteRequest = RegInit(0.U.asTypeOf(enqueue.bits))
+  val s3BypassData: UInt = RegInit(0.U.asTypeOf(UInt(parameter.datapathWidth.W)))
+  val dataInS3: UInt = maskAnd(s3Valid, indexToOH(s3Pipe.instructionIndex, parameter.chainingSize)).asUInt
+  val fwd3: Bool = RegInit(false.B)
+
+  val s2Valid: Bool = RegInit(false.B)
+  val s2Pipe: VRFWriteRequest = RegInit(0.U.asTypeOf(enqueue.bits))
+  val s2BypassData: UInt = RegInit(0.U.asTypeOf(UInt(parameter.datapathWidth.W)))
+  val s2EnqHitS1: Bool = RegInit(false.B)
+  val dataInS2: UInt = maskAnd(s2Valid, indexToOH(s2Pipe.instructionIndex, parameter.chainingSize)).asUInt
+  val fwd2: Bool = RegInit(false.B)
+
+  val s1Valid: Bool = RegInit(false.B)
+  val s1Pipe: VRFWriteRequest = RegInit(0.U.asTypeOf(enqueue.bits))
+  val s1BypassData: UInt = RegInit(0.U.asTypeOf(UInt(parameter.datapathWidth.W)))
+  val s1EnqHitS1: Bool = RegInit(false.B)
+  val s1EnqHitS2: Bool = RegInit(false.B)
+  val dataInS1: UInt = maskAnd(s1Valid, indexToOH(s1Pipe.instructionIndex, parameter.chainingSize)).asUInt
+  val fwd1: Bool = RegInit(false.B)
+
+  val s3EnqReady: Bool = dequeueWire.ready || !s3Valid
+  val s3Fire: Bool = s3EnqReady && s2Valid
+
+  val s2EnqReady: Bool = s3EnqReady || !s2Valid
+  val s2Fire: Bool = s2EnqReady && s1Valid
+
+  val s1EnqReady: Bool = Wire(Bool())
+  enqueue.ready := s1EnqReady
+  val s1Fire: Bool = enqueue.fire
+
   // raw forward
-  val hitWrite: Bool = Wire(Bool())
+  val enqHitS1: Bool = s1Valid && address(enqueue.bits) === address(s1Pipe)
+  val enqHitS2: Bool = s2Valid && address(enqueue.bits) === address(s2Pipe)
+  val enqHitS3: Bool = s3Valid && address(enqueue.bits) === address(s3Pipe)
+  val hitQueue: Bool = dequeueQueue.io.count =/= 0.U &&
+    address(enqueue.bits) === address(dequeueQueue.io.deq.bits)
+  val fwd: Bool = enqHitS1 || enqHitS2 || enqHitS3
+  s1EnqReady := (s2EnqReady || !s1Valid) && !hitQueue
+  val dataInQueue: UInt = maskAnd(dequeueQueue.io.count =/= 0.U,
+    indexToOH(dequeueQueue.io.deq.bits.instructionIndex, parameter.chainingSize)).asUInt
 
+  val enqNeedRead: Bool = !enqueue.bits.mask.andR && !fwd
   // 需要这个读端口完全ready
-  val readBeforeWrite: Bool = enqueue.fire && !enqueue.bits.mask.andR
-  vrfReadRequest.valid := readBeforeWrite && !hitWrite
+  val readBeforeWrite: Bool = enqueue.fire && enqNeedRead
+  vrfReadRequest.valid := readBeforeWrite
   vrfReadRequest.bits.vs := enqueue.bits.vd
   vrfReadRequest.bits.readSource := 2.U
   vrfReadRequest.bits.offset := enqueue.bits.offset
   vrfReadRequest.bits.instructionIndex := enqueue.bits.instructionIndex
-  // latch data
-  val readNext: Bool = RegNext(readBeforeWrite, false.B)
-  val dataFromWrite: Bool = RegNext(hitWrite, false.B)
-  val writeNext: UInt = RegNext(dequeue.bits.data, 0.U)
-  val readDataSelect: UInt = Mux(dataFromWrite, writeNext, vrfReadResult)
-  val dataReg: UInt = RegEnable(readDataSelect, 0.U(parameter.datapathWidth.W), readNext)
-  val latchDataSelect: UInt = Mux(readNext, readDataSelect, dataReg)
-
-  val pipeValid: Bool = RegInit(false.B)
-  val enqueuePipe: VRFWriteRequest = RegEnable(enqueue.bits, 0.U.asTypeOf(enqueue.bits), enqueue.fire)
-  val writeQueue: Queue[VRFWriteRequest] = Module(new Queue(chiselTypeOf(enqueue.bits), entries = 1, flow = true))
-  dequeue <> writeQueue.io.deq
-  writeQueue.io.enq.valid := pipeValid
-  writeQueue.io.enq.bits := enqueuePipe
-  val maskFill: UInt = FillInterleaved(8, enqueuePipe.mask)
-  writeQueue.io.enq.bits.data := enqueuePipe.data & maskFill | (latchDataSelect & (~maskFill))
-  maskedWrite1H :=
-    Mux(writeQueue.io.deq.valid, indexToOH(writeQueue.io.deq.bits.instructionIndex, parameter.chainingSize), 0.U) |
-      Mux(pipeValid, indexToOH(enqueuePipe.instructionIndex, parameter.chainingSize), 0.U)
-  enqueue.ready := !pipeValid || writeQueue.io.enq.ready
-  when(enqueue.fire ^ writeQueue.io.enq.fire) {
-    pipeValid := enqueue.fire
+
+  val vrfReadPipe: Queue[UInt] = Module(new Queue(
+    UInt(parameter.datapathWidth.W),
+    parameter.vrfParam.vrfReadLatency + 2))
+
+  val readDataValid: Bool = Pipe(
+    readBeforeWrite,
+    false.B,
+    parameter.vrfParam.vrfReadLatency
+  ).valid
+
+  vrfReadPipe.io.enq.valid := readDataValid
+  vrfReadPipe.io.enq.bits := vrfReadResult
+
+  maskedWrite1H := dataInS3 | dataInS2 | dataInS1 | dataInQueue
+
+  val maskFill: UInt = FillInterleaved(8, s3Pipe.mask)
+  val readDataSelect = Mux(fwd3, s3BypassData, vrfReadPipe.io.deq.bits)
+  val s3ReadFromVrf: Bool = !s3Pipe.mask.andR && !fwd3
+  dequeueWire.valid := s3Valid
+  dequeueWire.bits := s3Pipe
+  dequeueWire.bits.data := s3Pipe.data & maskFill | (readDataSelect & (~maskFill))
+  vrfReadPipe.io.deq.ready := dequeueWire.fire && s3ReadFromVrf
+
+  // update s1 reg
+  when(s1Fire) {
+    s1BypassData := dequeueWire.bits.data
+    s1EnqHitS1 := enqHitS1
+    s1EnqHitS2 := enqHitS2
+    fwd1 := fwd
+    s1Pipe := enqueue.bits
+  }
+  when(s1Fire ^ s2Fire) {
+    s1Valid := s1Fire
+  }
+
+  // update s2 reg
+  when(s2Fire) {
+    s2BypassData := Mux(s1EnqHitS2, dequeueWire.bits.data, s1BypassData)
+    s2EnqHitS1 := s1EnqHitS1
+    fwd2 := fwd1
+    s2Pipe := s1Pipe
+  }
+  when(s2Fire ^ s3Fire) {
+    s2Valid := s2Fire
+  }
+
+  // update s3 reg
+  when(s3Fire) {
+    s3BypassData := Mux(s2EnqHitS1, dequeueWire.bits.data, s2BypassData)
+    fwd3 := fwd2
+    s3Pipe := s2Pipe
+  }
+  when(s3Fire ^ dequeueWire.fire) {
+    s3Valid := s3Fire
   }
-  hitWrite := writeQueue.io.deq.valid &&
-    (writeQueue.io.deq.bits.vd === enqueue.bits.vd) &&
-    (writeQueue.io.deq.bits.offset === enqueue.bits.offset)
+  dequeue <> dequeueQueue.io.deq
 }

t1/src/laneStage/VrfReadPipe.scala

@@ -6,7 +6,7 @@ package org.chipsalliance.t1.rtl.lane
 import chisel3._
 import chisel3.experimental.hierarchy.{instantiable, public}
 import chisel3.util._
-import org.chipsalliance.t1.rtl.{LaneParameter, VRFReadQueueEntry, VRFReadRequest}
+import org.chipsalliance.t1.rtl.{DataPipeInReadStage, LaneParameter, VRFReadQueueEntry, VRFReadRequest}
 
 @instantiable
 class VrfReadPipe(parameter: LaneParameter, arbitrate: Boolean = false) extends Module {
@@ -42,30 +42,25 @@ class VrfReadPipe(parameter: LaneParameter, arbitrate: Boolean = false) extends
 
   (Seq(enqueue) ++ contender).zip(reqArbitrate.io.in).foreach { case (source, sink) => sink <> source }
 
-  val dataStageFree = Wire(Bool())
   // access read port
-  vrfReadRequest.valid := reqArbitrate.io.out.valid && dataStageFree
+  vrfReadRequest.valid := reqArbitrate.io.out.valid && dequeue.ready
   vrfReadRequest.bits.vs := reqArbitrate.io.out.bits.vs
   vrfReadRequest.bits.readSource := reqArbitrate.io.out.bits.readSource
   vrfReadRequest.bits.offset := reqArbitrate.io.out.bits.offset
   vrfReadRequest.bits.instructionIndex := reqArbitrate.io.out.bits.instructionIndex
-  reqArbitrate.io.out.ready := dataStageFree && vrfReadRequest.ready
+  reqArbitrate.io.out.ready := dequeue.ready && vrfReadRequest.ready
 
-  // read pipe stage1
-  val readPortFire: Bool = vrfReadRequest.fire
-  val stage1Valid: Bool = RegInit(false.B)
-  val ReadFireNext: Bool = RegNext(readPortFire)
-  val dataReg: UInt = RegEnable(vrfReadResult, 0.U(parameter.datapathWidth.W), ReadFireNext)
-  val stage1Choose: Option[Bool] = Option.when(arbitrate)(RegEnable(enqueue.fire, false.B, readPortFire))
+  val vrfReadLatency = parameter.vrfParam.vrfReadLatency
+  val dataQueue = Module(new Queue(new DataPipeInReadStage(parameter.datapathWidth, arbitrate), vrfReadLatency + 2))
+  val dataResponsePipe = Pipe(vrfReadRequest.fire, enqueue.fire, vrfReadLatency)
 
-  stage1Choose.foreach {d => when(readPortFire) { d := enqueue.fire}}
-  when(readPortFire ^ dequeue.fire) {
-    stage1Valid := readPortFire
-  }
+  dataQueue.io.enq.valid := dataResponsePipe.valid
+  dataQueue.io.enq.bits.data := vrfReadResult
+  dataQueue.io.enq.bits.choose.foreach(_ := dataResponsePipe.bits)
+  assert(!dataQueue.io.enq.valid || dataQueue.io.enq.ready, "queue overflow")
 
-  dataStageFree := !stage1Valid || dequeue.ready
-
-  dequeueChoose.zip(stage1Choose).foreach { case (io, data) => io := data }
-  dequeue.valid := stage1Valid
-  dequeue.bits := Mux(ReadFireNext, vrfReadResult, dataReg)
+  dequeueChoose.foreach { _ := dataQueue.io.deq.bits.choose.get }
+  dequeue.valid := dataQueue.io.deq.valid
+  dequeue.bits := dataQueue.io.deq.bits.data
+  dataQueue.io.deq.ready := dequeue.ready
 }

t1/src/lsu/Bundle.scala

@@ -65,4 +65,5 @@ class SimpleAccessStage1(param: MSHRParam) extends Bundle {
 
   // 访问l2的地址
   val address: UInt = UInt(param.paWidth.W)
+  val readData: UInt = UInt(param.datapathWidth.W)
 }