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[tests] bump rvv-codegen #901

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merged 7 commits into from
Dec 26, 2024
+983 −969
Merged

[tests] bump rvv-codegen #901

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4b93a82
[tests] bump rvv-codegen
Avimitin Dec 16, 2024
1bef4b7
[nix] remove legacy 'rvv-codegen' naming
Avimitin Dec 17, 2024
69193cc
[tests] set floa16 to false for all codegen cases
Avimitin Dec 17, 2024
f2b4168
[difftest] fix a bug in memory map route
FanShupei Dec 18, 2024
5d7ebfe
[ci] update t1 test case cycle data
invalid-email-address Dec 18, 2024
1f01c1a
[tests] update test env macro
Avimitin Dec 25, 2024
212d6e7
[t1rocketemu] increase sram size to 16M
Avimitin Dec 25, 2024
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990 changes: 495 additions & 495 deletions .github/designs/blastoise/t1rocketemu.json
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858 changes: 429 additions & 429 deletions .github/designs/rookidee/t1rocketemu.json
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4 changes: 2 additions & 2 deletions difftest/dpi_t1rocketemu/src/interconnect.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,7 @@ impl AddressSpace {
for (idx, dev) in self.devices.iter().enumerate() {
let (base, size) = dev.base_and_size;
if base <= addr && addr - base < size {
return if addr - base + len < size {
return if addr - base + len <= size {
Some(idx)
} else {
None
Expand All @@ -201,7 +201,7 @@ pub fn create_emu_addrspace() -> (AddressSpace, ExitFlagRef) {
const DDR_BASE: u32 = 0x2000_0000;
const DDR_SIZE: u32 = 0xa000_0000;
const SRAM_BASE: u32 = 0xc000_0000;
const SRAM_SIZE: u32 = 0x0040_0000;
const SRAM_SIZE: u32 = 0x0100_0000;

const SIMCTRL_BASE: u32 = 0x1000_0000;
const SIMCTRL_SIZE: u32 = 0x0000_1000; // one page
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2 changes: 1 addition & 1 deletion nix/overlay.nix
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ rec {

fetchMillDeps = final.callPackage ./pkgs/mill-builder.nix { };
circt-full = final.callPackage ./pkgs/circt-full.nix { };
rvv-codegen = final.callPackage ./pkgs/rvv-codegen.nix { };
riscv-vector-test = final.callPackage ./pkgs/riscv-vector-test.nix { };
add-determinism = final.callPackage ./pkgs/add-determinism { }; # faster strip-undetereminism

snps-fhs-env = final.callPackage ./pkgs/snps-fhs-env.nix { };
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22 changes: 22 additions & 0 deletions nix/pkgs/riscv-vector-test.nix
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@@ -0,0 +1,22 @@
{ fetchFromGitHub, buildGoModule }:
buildGoModule {
pname = "riscv-vector-test";
version = "unstable-2024-12-16";
src = fetchFromGitHub {
owner = "chipsalliance";
repo = "riscv-vector-tests";
rev = "52ccb798b355d4442f5d86a710e6bfa0eeb20cc2";
hash = "sha256-vfr7iMkqy3QUjkfM1by4RYUMpPHIsOk0XZSW8Big39s=";
fetchSubmodules = true;
};
doCheck = false;
vendorHash = "sha256-1A5yCj9AJHp9tcUIpLKamXn4Tl3KPFEtzke5X7h6V+4=";
# Get rid of copying the whole source
postInstall = ''
cp -r $src/configs $out/configs

mkdir $out/include
cp env/riscv-test-env/encoding.h $out/include
'';
}

29 changes: 0 additions & 29 deletions nix/pkgs/rvv-codegen.nix
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10 changes: 6 additions & 4 deletions tests/codegen/default.nix
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{ lib
, linkerScript
, rvv-codegen
, riscv-vector-test
, makeBuilder
# Instead of testing feature is supported on TOP level,
# codegen case are always generated with supported code.
Expand All @@ -18,20 +18,22 @@ let

includeArgs = [
"-I${./include}"
"-I${rvv-codegen}/include"
"-I${riscv-vector-test}/include"
];

dontUnpack = true;

buildPhase = ''
runHook preBuild

${rvv-codegen}/bin/single \
# Golang only accept "-flag=value" pattern to set value for flag, don't mess around with other cmd line option.
${riscv-vector-test}/bin/single \
-VLEN "${builtins.toString rtlDesignMetadata.vlen}" \
-XLEN "${builtins.toString rtlDesignMetadata.xlen}" \
-float16=false \
-repeat 16 \
-testfloat3level 2 \
-configfile ${rvv-codegen}/configs/${rawCaseName}.toml \
-configfile ${riscv-vector-test}/configs/${rawCaseName}.toml \
-outputfile $pname.S

# temporary fix, to be extended later
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21 changes: 13 additions & 8 deletions tests/codegen/include/riscv_test.h
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Expand Up @@ -16,14 +16,14 @@
RVTEST_FP_ENABLE; \
.endm

#define RVTEST_RV64UV \
.macro init; \
RVTEST_VECTOR_ENABLE; \
#define RVTEST_RV64UV \
.macro init; \
RVTEST_VECTOR_ENABLE; \
.endm

#define RVTEST_RV64UFV \
#define RVTEST_RV64UVX \
.macro init; \
RVTEST_FP_VECTOR_ENABLE; \
RVTEST_ZVE32X_ENABLE; \
.endm

#define RVTEST_RV32U \
Expand All @@ -40,6 +40,11 @@
RVTEST_VECTOR_ENABLE; \
.endm

#define RVTEST_RV32UVX \
.macro init; \
RVTEST_ZVE32X_ENABLE; \
.endm

#define INIT_XREG \
li x1, 0; \
li x2, 0; \
Expand Down Expand Up @@ -115,14 +120,14 @@
csrs mstatus, a0; \
csrwi fcsr, 0

#define RVTEST_FP_VECTOR_ENABLE \
#define RVTEST_VECTOR_ENABLE \
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1)); \
csrs mstatus, a0; \
csrwi fcsr, 0; \
csrwi vcsr, 0;

#define RVTEST_VECTOR_ENABLE \
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1)); \
#define RVTEST_ZVE32X_ENABLE \
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)); \
csrs mstatus, a0; \
csrwi vcsr, 0;

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10 changes: 10 additions & 0 deletions tests/riscv-test-env/p/riscv_test.h
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Expand Up @@ -23,6 +23,11 @@
RVTEST_VECTOR_ENABLE; \
.endm

#define RVTEST_RV64UVX \
.macro init; \
RVTEST_ZVE32X_ENABLE; \
.endm

#define RVTEST_RV32U \
.macro init; \
.endm
Expand All @@ -37,6 +42,11 @@
RVTEST_VECTOR_ENABLE; \
.endm

#define RVTEST_RV32UVX \
.macro init; \
RVTEST_ZVE32X_ENABLE; \
.endm

#define RVTEST_RV64M \
.macro init; \
RVTEST_ENABLE_MACHINE; \
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4 changes: 4 additions & 0 deletions tests/riscv-test-env/v/riscv_test.h
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,10 @@
csrwi fcsr, 0; \
csrwi vcsr, 0;

#undef RVTEST_ZVE32X_ENABLE
#define RVTEST_ZVE32X_ENABLE \
csrwi vcsr, 0;

#undef RVTEST_CODE_BEGIN
#define RVTEST_CODE_BEGIN \
.text; \
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2 changes: 1 addition & 1 deletion tests/t1.ld
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Expand Up @@ -5,7 +5,7 @@ MEMORY {
SCALAR (RWX) : ORIGIN = 0x20000000, LENGTH = 512M /* put first to set it as default */
MMIO (RW) : ORIGIN = 0x00000000, LENGTH = 512M
DDR (RW) : ORIGIN = 0x40000000, LENGTH = 2048M
SRAM (RW) : ORIGIN = 0xc0000000, LENGTH = 4M /* TODO: read from config */
SRAM (RW) : ORIGIN = 0xc0000000, LENGTH = 16M /* TODO: read from config */
}

SECTIONS {
Expand Down