Skip to content

Home

Jump to bottom
Peter Wittich edited this page Aug 10, 2021 · 2 revisions

Welcome to the CM_FPGA_FW wiki!

Summer test chain information

  • Vivado version: 2020.1
  • Base FW repo: CM_FPGA_FW (this repo), which is a fork off the apollo-lhc version of the same repo
  • branch: feature/summerchain, which is a branch off develop
  • branch of firmware-hls repo: reduced_config_pr

Build instructions

See the requirements in the readme file. The build is makefile-based with lots of tcl files. Right now the project DOES NOT BUILD TO COMPLETION.

The build typically takes one argument (which CM and FPGA you are building for.) We are using the VU7P, either in -1 speed grade (Cornell) or -2 speed grade (TIF). The Zynq is 7-series.

The firmware-hls repo is a git submodule of this repo. You need to build the xci files for the firmware-hls module in a separate step; see the following readme in the HLS repo for instructions on how to build the HLS repo.

A full set of commands to build the project are below. This assumes you've already set up the requirements as documented in the first readme above, including the vivado version.

git clone [email protected]:cms-L1TK/CM_FPGA_FW.git
cd CM_FPGA_FW
git checkout feature/summerchain
make init
pushd src/tracktrigger/IntegrationTests/ReducedConfigPR/script/
./compileHLS.sh
vivado -mode tcl -source ./makeProject.tcl
vivado -mode tcl -source ../../common/script/synth.tcl
popd
make Cornell_rev1_p2_VU7p-1-SM_7s

The make init step initializes all git submodules, including the firmware-hls repo which is a submodule of this module, found in src/tracktrigger. The three commands after the pushd compile the IP in the firmware-hls repo. The final make command is to build the bit file for the project.

The configuration files for the project are in config/Cornell_rev1_p2_VU7p-1-SM_7s. In particular, files.tcl lists all files to be included in the project, including all the xci files from the HLS build. The top-level file is located in configs/Cornell_rev1_p2_VU7p-1-SM_7s/src/top.vhd. The build creates a xpr file and fails after synthesis.

Open Issues

  • all memory VHDL files must be manually set to VHDL2008 (pw to fix)
  • SectorProcessor top level module is not connected to I/O
Clone this wiki locally