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Merge pull request #2 from thomaslenzi/master
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Bring changes from tlenzi into cms-gem-daq-project
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@jsturdy
jsturdy committed Feb 13, 2015
2 parents 761a068 + 6bca889 commit 246f3fd
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Showing 115 changed files with 247,091 additions and 229,943 deletions.
8 changes: 4 additions & 4 deletions .../glib_v3/fw/fpga/prj/glib_fw/BPIFlash.cfi → ...lib_v3/fw/fpga/prj/glib_fw/GLIB_Flash.cfi
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Expand Up @@ -2,10 +2,10 @@
# Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

SOFTWARE_VERSION P.20131013
DATE 11/24/2014 - 10:50
SOURCE \\psf\home\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw\BPIFlash.mcs
DATE 02/13/2015 - 09:20
SOURCE \\psf\home\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw\GLIB_Flash.mcs
DEVICE 16384K
DATA_WIDTH 16
FILL_DATA 0xFF
SIGNATURE 0xD6E69199
START_ADDRESS 0x00000000 END_ADDRESS 0x002A20AB DIRECTION_UP "Z:/Documents/PhD/Code/GLIB/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bit" 6vlx130tff1156
SIGNATURE 0xD52342F0
START_ADDRESS 0x00000000 END_ADDRESS 0x002BEF27 DIRECTION_UP "Z:/Documents/PhD/Code/GLIB/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bit" 6vlx130tff1156
268,109 changes: 137,755 additions & 130,354 deletions .../glib_v3/fw/fpga/prj/glib_fw/BPIFlash.mcs → ...lib_v3/fw/fpga/prj/glib_fw/GLIB_Flash.mcs
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8 changes: 4 additions & 4 deletions .../glib_v3/fw/fpga/prj/glib_fw/BPIFlash.prm → ...lib_v3/fw/fpga/prj/glib_fw/GLIB_Flash.prm
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Original file line number Diff line number Diff line change
@@ -1,17 +1,17 @@
PROMGEN: Xilinx Prom Generator P.20131013
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

promgen -w -p mcs -c FF -o Z:\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw\//BPIFlash -x xcf128x -u 00000000 Z:/Documents/PhD/Code/GLIB/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bit -bpi_dc parallel -data_width 16
promgen -w -p mcs -c FF -o Z:\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw//GLIB_Flash -x xcf128x -u 00000000 Z:/Documents/PhD/Code/GLIB/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bit -bpi_dc parallel -data_width 16

PROM \\psf\home\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw\BPIFlash.prm map: Mon Nov 24 10:50:35 2014
PROM \\psf\home\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw\GLIB_Flash.prm map: Fri Feb 13 09:20:47 2015

Calculating PROM checksum with fill value ff

Format Mcs86 (32-bit)
Size 16384K
PROM start 0000:0000
PROM end 00ff:ffff
PROM checksum d6e69199
PROM checksum d52342f0

Addr1 Addr2 Date File(s)
0000:0000 002a:20ab Nov 24 10:46:21 2014 Z:/Documents/PhD/Code/GLIB/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bit
0000:0000 002b:ef27 Dec 01 11:33:20 2014 Z:/Documents/PhD/Code/GLIB/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bit
4 changes: 2 additions & 2 deletions amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/_ngo/netlist.lst
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@@ -1,5 +1,5 @@
Z:\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw\glib_top.ngc 1416987147
ipcore_dir/tracking_data_fifo.ngc 1416467750
Z:\Documents\PhD\Code\GLIB\amc_glib\trunk\glib_v3\fw\fpga\prj\glib_fw\glib_top.ngc 1417429405
ipcore_dir/tracking_data_fifo.ngc 1417018618
ipcore_dir/trigger_data_fifo.ngc 1416312836
../../src/system/ethernet/ipcore_dir/basex/v6_emac_v2_3_basex.ngc 1403509420
../../src/system/ethernet/ipcore_dir/sgmii/v6_emac_v2_3_sgmii.ngc 1403509420
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82 changes: 41 additions & 41 deletions amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/_xmsgs/map.xmsgs
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26 changes: 13 additions & 13 deletions amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/_xmsgs/par.xmsgs
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Original file line number Diff line number Diff line change
Expand Up @@ -91,46 +91,46 @@
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">amc_port_tx_in&lt;19&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMC_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram2_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMC_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram2_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram2_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram2_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram2_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMC_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/sfp_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram2_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMC_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/ctrl_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram3_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">system/gbt_phase_monitoring/fmc1_cdce_pm/status_dpram/U0/xst_options.dist_mem_inst/gen_sdp_ram.sdpram_inst/Mram_ram2_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>

<msg type="info" file="Route" num="501" delta="old" >One or more directed routing (DIRT) constraints generated for a specific device have been found. Note that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail, verify that the same connectivity is available in the target device for this implementation.
Expand Down
24 changes: 14 additions & 10 deletions amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_fw.gise
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Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,8 @@
<branch xil_pn:name="Implementation"/>
<branch xil_pn:name="BehavioralSim"/>
</file>
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
Expand Down Expand Up @@ -130,7 +132,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1416498264" xil_pn:in_ck="-6981639143270318303" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-738508652297565762" xil_pn:start_ts="1416498256">
<transform xil_pn:end_ts="1417018680" xil_pn:in_ck="-6981639143270318303" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-738508652297565762" xil_pn:start_ts="1417018672">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../src/system/cdce/cdce_phase_mon_v2/dpram/ttclk_distributed_dpram.ngc"/>
Expand Down Expand Up @@ -174,7 +176,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1416987153" xil_pn:in_ck="-8588165163509781149" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="-1895621303767648803" xil_pn:start_ts="1416986976">
<transform xil_pn:end_ts="1417429408" xil_pn:in_ck="-8588165163509781149" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="-1895621303767648803" xil_pn:start_ts="1417429244">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
Expand All @@ -196,7 +198,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1416987223" xil_pn:in_ck="-2150822889573372828" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2015394535562358994" xil_pn:start_ts="1416987153">
<transform xil_pn:end_ts="1417429450" xil_pn:in_ck="-2150822889573372828" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2015394535562358994" xil_pn:start_ts="1417429408">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
Expand All @@ -206,7 +208,7 @@
<outfile xil_pn:name="glib_top.ngd"/>
<outfile xil_pn:name="glib_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1416987470" xil_pn:in_ck="-6875985122728476490" xil_pn:name="TRANEXT_map_virtex6" xil_pn:prop_ck="3468729705812694747" xil_pn:start_ts="1416987223">
<transform xil_pn:end_ts="1417429677" xil_pn:in_ck="-6875985122728476490" xil_pn:name="TRANEXT_map_virtex6" xil_pn:prop_ck="3468729705812694747" xil_pn:start_ts="1417429450">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
Expand All @@ -222,7 +224,7 @@
<outfile xil_pn:name="glib_top_summary.xml"/>
<outfile xil_pn:name="glib_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1416987668" xil_pn:in_ck="4417934387119617455" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-174231212644676884" xil_pn:start_ts="1416987470">
<transform xil_pn:end_ts="1417429895" xil_pn:in_ck="4417934387119617455" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-174231212644676884" xil_pn:start_ts="1417429677">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
Expand All @@ -237,7 +239,7 @@
<outfile xil_pn:name="glib_top_pad.txt"/>
<outfile xil_pn:name="glib_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1416987776" xil_pn:in_ck="5376262738270210579" xil_pn:name="TRANEXT_bitFile_virtex6" xil_pn:prop_ck="2793798927870611753" xil_pn:start_ts="1416987668">
<transform xil_pn:end_ts="1417430007" xil_pn:in_ck="5376262738270210579" xil_pn:name="TRANEXT_bitFile_virtex6" xil_pn:prop_ck="2793798927870611753" xil_pn:start_ts="1417429895">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
Expand All @@ -250,21 +252,23 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1416988053" xil_pn:in_ck="5376262738270197725" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="7885344654059281841" xil_pn:start_ts="1416988050">
<transform xil_pn:end_ts="1423815189" xil_pn:in_ck="5376262738270197725" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="7885344654059281841" xil_pn:start_ts="1423815174">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
</transform>
<transform xil_pn:end_ts="1416987604" xil_pn:in_ck="5376262738270210579" xil_pn:name="TRAN_asynDlyRpt" xil_pn:start_ts="1416987568">
<transform xil_pn:end_ts="1417429828" xil_pn:in_ck="5376262738270210579" xil_pn:name="TRAN_asynDlyRpt" xil_pn:start_ts="1417429786">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="glib_top.dly"/>
</transform>
<transform xil_pn:end_ts="1416987629" xil_pn:in_ck="5376262738270210579" xil_pn:name="TRAN_clkRegionRpt" xil_pn:start_ts="1416987604">
<transform xil_pn:end_ts="1417429856" xil_pn:in_ck="5376262738270210579" xil_pn:name="TRAN_clkRegionRpt" xil_pn:start_ts="1417429828">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="glib_top.clk_rgn"/>
</transform>
<transform xil_pn:end_ts="1416987668" xil_pn:in_ck="-7845735148674692430" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1416987629">
<transform xil_pn:end_ts="1417429895" xil_pn:in_ck="-7845735148674692430" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1417429856">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
Expand Down
4 changes: 2 additions & 2 deletions amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bgn
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ C:\Xilinx\14.7\ISE_DS\ISE\.
-1
Opened constraints file glib_top.pcf.

Wed Nov 26 08:41:19 2014
Mon Dec 01 11:31:48 2014

C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -d -g Binary:no -g Compress -g CRC:Enable -g ConfigRate:50 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g HswapenPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g Disable_JTAG:No -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ConfigFallback:Enable -g BPI_page_size:1 -g OverTempPowerDown:Disable -g USR_ACCESS:None -g next_config_addr:None -g JTAG_SysMon:Enable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No glib_top.ncd

Expand Down Expand Up @@ -158,5 +158,5 @@ Xilinx software updates or new releases.

Creating bit map...
Saving bit stream in "glib_top.bit".
Bitstream compression saved 21632736 bits.
Bitstream compression saved 20685568 bits.
Bitstream generation is complete.
Binary file modified amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bit
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12 changes: 6 additions & 6 deletions amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/glib_top.bld
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
../../src/system/pcie/sys_pcie/ezdma2_ipbus_int/cores/slv_rd_fifo -sd
../../src/system/pcie/sys_pcie/ezdma2_ipbus_int/cores/slv_wr_fifo -sd
../../src/system/cdce/cdce_phase_mon_v2/pll -sd ../../src/system/pll -nt
timestamp -uc src/system.ucf -uc src/system_clk.ucf -uc src/gtx.ucf -p
timestamp -uc src/gtx.ucf -uc src/system_clk.ucf -uc src/system.ucf -p
xc6vlx130t-ff1156-1 glib_top.ngc glib_top.ngd

Reading NGO file
Expand All @@ -28,9 +28,9 @@ Loading design module
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "src/system.ucf" ...
Annotating constraints to design from ucf file "src/system_clk.ucf" ...
Annotating constraints to design from ucf file "src/gtx.ucf" ...
Annotating constraints to design from ucf file "src/system_clk.ucf" ...
Annotating constraints to design from ucf file "src/system.ucf" ...
WARNING:NgdBuild - The value of SIM_DEVICE on instance
'system/amc_p0_en.amc_p0_eth/clkbuf' of type BUFR has been changed from
'VIRTEX4' to 'VIRTEX6' to correct post-ngdbuild and timing simulation for
Expand Down Expand Up @@ -10056,10 +10056,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 5255

Total memory usage is 316424 kilobytes
Total memory usage is 319880 kilobytes

Writing NGD file "glib_top.ngd" ...
Total REAL time to NGDBUILD completion: 47 sec
Total CPU time to NGDBUILD completion: 29 sec
Total REAL time to NGDBUILD completion: 32 sec
Total CPU time to NGDBUILD completion: 30 sec

Writing NGDBUILD log file "glib_top.bld"...
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