8 November 2014 - 20h45 - Synthetized, missing T1, not tested

cms-gem-daq-project · Nov 8, 2014 · d2b33ce · d2b33ce
1 parent f8c1f91
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diff --git a/...v3/fw/fpga/prj/glib_fw/.Xil/PlanAhead-1808-Thomas-Lenzi-PC/ngc2edif/_xmsgs/ngc2edif.xmsgs b/...v3/fw/fpga/prj/glib_fw/.Xil/PlanAhead-1808-Thomas-Lenzi-PC/ngc2edif/_xmsgs/ngc2edif.xmsgs
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="NetListWriters" num="298" delta="new" >No output is written to <arg fmt="%s" index="1">ttclk_distributed_dpram.xncf</arg>, ignored.
+</msg>
+
+</messages>
+