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[CORE] [RISCV] Fix needed for riscv64 #45574

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merged 1 commit into from
Jul 31, 2024
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[CORE] [RISCV] Fix needed for riscv64 #45574

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5 changes: 5 additions & 0 deletions FWCore/Services/plugins/CPU.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,8 @@
#include "cpu_features/cpuinfo_aarch64.h"
#elif defined(CPU_FEATURES_ARCH_PPC)
#include "cpu_features/cpuinfo_ppc.h"
#elif defined(CPU_FEATURES_ARCH_RISCV)
#include "cpu_features/cpuinfo_riscv.h"
#endif

#include <cstdlib>
Expand Down Expand Up @@ -253,6 +255,9 @@ namespace edm {
#elif defined(CPU_FEATURES_ARCH_PPC)
const auto strings{GetPPCPlatformStrings()};
model = strings.machine;
#elif defined(CPU_FEATURES_ARCH_RISCV)
const auto info{GetRiscvInfo()};
model = fmt::format("riscv64 {} {}", info.vendor, info.uarch);
#endif
return model;
}
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6 changes: 6 additions & 0 deletions FWCore/Utilities/interface/HRRealTime.h
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Expand Up @@ -76,6 +76,12 @@ namespace edm {
__asm__ __volatile__("isb; mrs %0, cntvct_el0" : "=r"(ret));
return ret;
}
#elif defined(__riscv) && __riscv_xlen == 64
static __inline__ unsigned long long rdtsc(void) {
unsigned long long cycles;
asm volatile("rdcycle %0" : "=r"(cycles));
return cycles;
}
#else
#error The file FWCore/Utilities/interface/HRRealTime.h needs to be set up for your CPU type.
#endif
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