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SSE and FPU support #410

Merged
merged 6 commits into from
Oct 25, 2024
Merged

SSE and FPU support #410

merged 6 commits into from
Oct 25, 2024

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vsntk18
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@vsntk18 vsntk18 commented Jul 15, 2024

This PR entails following changes:

  1. Enable the usage of SSE/FPU instructions in SVSM.
  2. xstate management while switching between tasks.
  3. A couple of unit tests check the sse instruction usage and proper xstate management.

I will submit the related exception handling in another PR.

kernel/src/cpu/sse.rs Outdated Show resolved Hide resolved
kernel/src/cpu/sse.rs Outdated Show resolved Hide resolved
kernel/src/task/tasks.rs Outdated Show resolved Hide resolved
kernel/src/mm/vm/mapping/xsave_area.rs Outdated Show resolved Hide resolved
kernel/src/cpu/sse.rs Outdated Show resolved Hide resolved
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This goes into the right direction, thanks for the work! I marked some desired changes inline.

kernel/src/task/schedule.rs Outdated Show resolved Hide resolved
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vsntk18 commented Aug 22, 2024

Addressed the review comments.

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Thanks for updating the PR! I left a couple of review comments.

kernel/src/cpu/sse.rs Outdated Show resolved Hide resolved
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@joergroedel joergroedel added the wait-for-update PR is waiting to be updated to address review comments label Aug 23, 2024
@joergroedel joergroedel self-assigned this Aug 23, 2024
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vsntk18 commented Aug 30, 2024

Addressed review comments.

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vsntk18 commented Oct 21, 2024

Rebase done.

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What are the rules for FP/SSE in interrupt handlers? Is the interrupt dispatch logic required to save/restore FPU state to prevent reentrant corruption?

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What are the rules for FP/SSE in interrupt handlers? Is the interrupt dispatch logic required to save/restore FPU state to prevent reentrant corruption?

None of this is handled yet in this PR. The plan is that the kernel is in general not allowed to use the FPU at all. There will be calls to enable/disable FPU usage, that would save/restore the state, but will not be possible to be used in a nested way. This means that IRQ handlers are in general not allowed to use the FPU.

Some cpuid functions require a non-zero value of xcr0 to be
passed.

Signed-off-by: Vasant Karasulli <[email protected]>
Check for the available SSE/FPU related features and
initialize them.

Signed-off-by: Vasant Karasulli <[email protected]>
Reserve xsave area for tasks to manage xstate.

Signed-off-by: Vasant Karasulli <[email protected]>
use xsaveopt/xrstor instructions to save and restore task context.

Signed-off-by: Vasant Karasulli <[email protected]>
These in-svsm tests check if tasks can use some sse/fpu instructions
and xstate is saved/restored properly during task switches.

Signed-off-by: Vasant Karasulli <[email protected]>
This is a temporary solution until we have smart pointer.
This also gives a chance to move xsave/xrestor functionality
outside the assembly block.

Signed-off-by: Vasant Karasulli <[email protected]>
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The changes look ready for merging to me. There are still a few rough edges, but some of them need a better kernel initialization infrastructure first. So lets move on with this now. Thanks for taking on and driving this work forward, @vsntk18

@joergroedel joergroedel merged commit cc8b754 into coconut-svsm:main Oct 25, 2024
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4 participants