FlexiCAS: A Flexible Cache Architectural Simulator

GPL licensed.

Copyright (c) 2023-2024 Wei Song <[email protected]> at the Institute of Information Engineering, Chinese Academy of Sciences.

Authors:

• Wei Song (SKLOIS, Institute of Information Engineering, Chinese Academy of Sciences)
• Jinchi Han (SKLOIS, Institute of Information Engineering, Chinese Academy of Sciences)
• Zhidong Wang (SKLOIS, Institute of Information Engineering, Chinese Academy of Sciences)

Features

• A pure C++ (std c++17) implementation of a modular cache architecture.
• Modular support for different index function, replacement policy, and slice mapping function.
• Modular support for complex cache array structure, such as separated metadata and data arrays.
• Modular support for different coherence protocols (MI/MSI/MESI), inclusing broadcast and directory.
• Modular support for inclusive/exclusive cache hierarchy.
• On-demand hooking up with user defined performance monitors.
• On-demand estimation of cache access delay (behavoral, not cycle accurate).

Note

The project is under active developing. Please raise issues or pull requests for any sugguestion or fix.

This is an overhual of a previous in-house implemented simulator, namely cache-model.

Usage

Right now, see the regression test cases in regression/*.cpp and try to run make regression.