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[euvm] Prefer using UBVEC than toubvec for constant bvec values
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@puneet
puneet committed Oct 10, 2023
1 parent cdbf82d commit f601f3e
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Showing 18 changed files with 757 additions and 670 deletions.
316 changes: 158 additions & 158 deletions euvm/riscv/gen/isa/riscv_b_instr.d
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170 changes: 85 additions & 85 deletions euvm/riscv/gen/isa/riscv_compressed_instr.d
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16 changes: 8 additions & 8 deletions euvm/riscv/gen/isa/riscv_csr_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ import riscv.gen.target: supported_isa;

import std.format: format;

import esdl.data.bvec: ubvec, toubvec, clog2;
import esdl.data.bvec: ubvec, UBVEC, clog2;
import esdl.rand: constraint, rand;
import uvm;

Expand Down Expand Up @@ -181,17 +181,17 @@ class riscv_csr_instr: riscv_instr
}

override ubvec!7 get_opcode() {
return toubvec!7(0b1110011);
return UBVEC!(7, 0b1110011);
}

override ubvec!3 get_func3() {
switch (instr_name) {
case riscv_instr_name_t.CSRRW: return toubvec!3(0b001);
case riscv_instr_name_t.CSRRS: return toubvec!3(0b010);
case riscv_instr_name_t.CSRRC: return toubvec!3(0b011);
case riscv_instr_name_t.CSRRWI: return toubvec!3(0b101);
case riscv_instr_name_t.CSRRSI: return toubvec!3(0b110);
case riscv_instr_name_t.CSRRCI: return toubvec!3(0b111);
case riscv_instr_name_t.CSRRW: return UBVEC!(3, 0b001);
case riscv_instr_name_t.CSRRS: return UBVEC!(3, 0b010);
case riscv_instr_name_t.CSRRC: return UBVEC!(3, 0b011);
case riscv_instr_name_t.CSRRWI: return UBVEC!(3, 0b101);
case riscv_instr_name_t.CSRRSI: return UBVEC!(3, 0b110);
case riscv_instr_name_t.CSRRCI: return UBVEC!(3, 0b111);
default: return super.get_func3();
}
}
Expand Down
6 changes: 3 additions & 3 deletions euvm/riscv/gen/isa/riscv_floating_point_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -262,13 +262,13 @@ class riscv_floating_point_instr: riscv_instr
}

override void set_imm_len() {
import esdl.data.bvec: toubvec;
import esdl.data.bvec: UBVEC;
if (instr_format == riscv_instr_format_t.CL_FORMAT ||
instr_format == riscv_instr_format_t.CS_FORMAT)
imm_len = toubvec!5(5);
imm_len = UBVEC!(5, 5);
if (instr_format == riscv_instr_format_t.CI_FORMAT ||
instr_format == riscv_instr_format_t.CSS_FORMAT)
imm_len = toubvec!5(6);
imm_len = UBVEC!(5, 6);
}

override void do_copy(uvm_object rhs) {
Expand Down
303 changes: 151 additions & 152 deletions euvm/riscv/gen/isa/riscv_instr.d
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46 changes: 23 additions & 23 deletions euvm/riscv/gen/isa/riscv_zba_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ import riscv.gen.target: supported_isa;

import std.format: format;

import esdl.data.bvec: ubvec, toubvec, clog2;
import esdl.data.bvec: ubvec, UBVEC, clog2;
import uvm;

import std.algorithm: canFind;
Expand All @@ -44,10 +44,10 @@ class riscv_zba_instr: riscv_instr

override void set_imm_len() {
if (instr_name != riscv_instr_name_t.SLLI_UW) {
imm_len = toubvec!5(clog2(XLEN) - 1);
imm_len = UBVEC!(5, clog2(XLEN) - 1);
}
else {
imm_len = toubvec!5(clog2(XLEN));
imm_len = UBVEC!(5, clog2(XLEN));
}
imm_mask = imm_mask << imm_len;
}
Expand All @@ -56,47 +56,47 @@ class riscv_zba_instr: riscv_instr
switch (instr_name) {
case riscv_instr_name_t.SH1ADD,
riscv_instr_name_t.SH2ADD,
riscv_instr_name_t.SH3ADD: return toubvec!7(0b0110011);
riscv_instr_name_t.SH3ADD: return UBVEC!(7, 0b0110011);
case riscv_instr_name_t.SH1ADD_UW,
riscv_instr_name_t.SH2ADD_UW,
riscv_instr_name_t.SH3ADD_UW: return toubvec!7(0b0111011);
case riscv_instr_name_t.SLLI_UW: return toubvec!7(0b0011011);
riscv_instr_name_t.SH3ADD_UW: return UBVEC!(7, 0b0111011);
case riscv_instr_name_t.SLLI_UW: return UBVEC!(7, 0b0011011);
default: return super.get_opcode();
}
}

override ubvec!3 get_func3() {
switch (instr_name) {
case riscv_instr_name_t.ADD_UW: return toubvec!3(0b000);
case riscv_instr_name_t.SH1ADD: return toubvec!3(0b010);
case riscv_instr_name_t.SH2ADD: return toubvec!3(0b100);
case riscv_instr_name_t.SH3ADD: return toubvec!3(0b110);
case riscv_instr_name_t.SH1ADD_UW: return toubvec!3(0b010);
case riscv_instr_name_t.SH2ADD_UW: return toubvec!3(0b100);
case riscv_instr_name_t.SH3ADD_UW: return toubvec!3(0b110);
case riscv_instr_name_t.SLLI_UW: return toubvec!3(0b001);
case riscv_instr_name_t.ADD_UW: return UBVEC!(3, 0b000);
case riscv_instr_name_t.SH1ADD: return UBVEC!(3, 0b010);
case riscv_instr_name_t.SH2ADD: return UBVEC!(3, 0b100);
case riscv_instr_name_t.SH3ADD: return UBVEC!(3, 0b110);
case riscv_instr_name_t.SH1ADD_UW: return UBVEC!(3, 0b010);
case riscv_instr_name_t.SH2ADD_UW: return UBVEC!(3, 0b100);
case riscv_instr_name_t.SH3ADD_UW: return UBVEC!(3, 0b110);
case riscv_instr_name_t.SLLI_UW: return UBVEC!(3, 0b001);
default: return super.get_func3();
}
}

override ubvec!7 get_func7() {
switch (instr_name) {
case riscv_instr_name_t.ADD_UW: return toubvec!7(0b0000100);
case riscv_instr_name_t.SH1ADD: return toubvec!7(0b0010000);
case riscv_instr_name_t.SH2ADD: return toubvec!7(0b0010000);
case riscv_instr_name_t.SH3ADD: return toubvec!7(0b0010000);
case riscv_instr_name_t.SH1ADD_UW: return toubvec!7(0b0010000);
case riscv_instr_name_t.SH2ADD_UW: return toubvec!7(0b0010000);
case riscv_instr_name_t.SH3ADD_UW: return toubvec!7(0b0010000);
case riscv_instr_name_t.SLLI_UW: return toubvec!7(0b0010000);
case riscv_instr_name_t.ADD_UW: return UBVEC!(7, 0b0000100);
case riscv_instr_name_t.SH1ADD: return UBVEC!(7, 0b0010000);
case riscv_instr_name_t.SH2ADD: return UBVEC!(7, 0b0010000);
case riscv_instr_name_t.SH3ADD: return UBVEC!(7, 0b0010000);
case riscv_instr_name_t.SH1ADD_UW: return UBVEC!(7, 0b0010000);
case riscv_instr_name_t.SH2ADD_UW: return UBVEC!(7, 0b0010000);
case riscv_instr_name_t.SH3ADD_UW: return UBVEC!(7, 0b0010000);
case riscv_instr_name_t.SLLI_UW: return UBVEC!(7, 0b0010000);
default: return super.get_func7();
}
}

override string convert2bin(string prefix = "") {
string binary = "";
if (instr_name == riscv_instr_name_t.SLLI_UW) {
binary = format("%8h", toubvec!5(0b0_0001) ~ cast(ubvec!7)(imm[0..6]) ~
binary = format("%8h", UBVEC!(5, 0b0_0001) ~ cast(ubvec!7)(imm[0..6]) ~
rs1 ~ get_func3() ~ rd ~ get_opcode());
}
else {
Expand Down
132 changes: 66 additions & 66 deletions euvm/riscv/gen/isa/riscv_zbb_instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ import riscv.gen.target: supported_isa;
import std.format: format;
import std.string: toLower;

import esdl.data.bvec: ubvec, toubvec, clog2;
import esdl.data.bvec: ubvec, toubvec, clog2, UBVEC;
import uvm;

import std.algorithm: canFind;
Expand Down Expand Up @@ -73,10 +73,10 @@ class riscv_zbb_instr: riscv_instr
override void set_imm_len() {
if (instr_format == riscv_instr_format_t.I_FORMAT) {
if (instr_name == riscv_instr_name_t.RORI) {
imm_len = toubvec!5(clog2(XLEN));
imm_len = UBVEC!(5, clog2(XLEN));
}
else {
imm_len = toubvec!5(5);
imm_len = UBVEC!(5, 5);
}
}
imm_mask = imm_mask << imm_len;
Expand Down Expand Up @@ -173,101 +173,101 @@ class riscv_zbb_instr: riscv_instr
riscv_instr_name_t.ORN,
riscv_instr_name_t.ROL,
riscv_instr_name_t.ROR,
riscv_instr_name_t.XNOR: return toubvec!7(0b011_0011);
riscv_instr_name_t.XNOR: return UBVEC!(7, 0b011_0011);
case riscv_instr_name_t.ZEXT_H:
return toubvec!7(0b011_0011 | (toubvec!7(is_rv64()) << 3));
return (UBVEC!(7, 0b011_0011) | (toubvec!7(is_rv64()) << 3));
case riscv_instr_name_t.ROLW,
riscv_instr_name_t.RORW: return toubvec!7(0b011_1011);
riscv_instr_name_t.RORW: return UBVEC!(7, 0b011_1011);
case riscv_instr_name_t.CLZ,
riscv_instr_name_t.CPOP,
riscv_instr_name_t.CTZ,
riscv_instr_name_t.ORC_B,
riscv_instr_name_t.CLZW,
riscv_instr_name_t.CPOPW,
riscv_instr_name_t.CTZW,
riscv_instr_name_t.RORIW: return toubvec!7(0b001_1011);
riscv_instr_name_t.RORIW: return UBVEC!(7, 0b001_1011);
case riscv_instr_name_t.REV8,
riscv_instr_name_t.RORI,
riscv_instr_name_t.SEXT_B,
riscv_instr_name_t.SEXT_H: return toubvec!7(0b001_0011);
riscv_instr_name_t.SEXT_H: return UBVEC!(7, 0b001_0011);
default: return super.get_opcode();
}
}

override ubvec!3 get_func3() {
switch (instr_name) {
case riscv_instr_name_t.ANDN: return toubvec!3(0b111);
case riscv_instr_name_t.CLZ: return toubvec!3(0b001);
case riscv_instr_name_t.CLZW: return toubvec!3(0b001);
case riscv_instr_name_t.CPOP: return toubvec!3(0b001);
case riscv_instr_name_t.CPOPW: return toubvec!3(0b001);
case riscv_instr_name_t.CTZ: return toubvec!3(0b001);
case riscv_instr_name_t.CTZW: return toubvec!3(0b001);
case riscv_instr_name_t.MAX: return toubvec!3(0b110);
case riscv_instr_name_t.MAXU: return toubvec!3(0b111);
case riscv_instr_name_t.MIN: return toubvec!3(0b100);
case riscv_instr_name_t.MINU: return toubvec!3(0b101);
case riscv_instr_name_t.ORC_B: return toubvec!3(0b101);
case riscv_instr_name_t.ORN: return toubvec!3(0b110);
case riscv_instr_name_t.REV8: return toubvec!3(0b101);
case riscv_instr_name_t.ROL: return toubvec!3(0b001);
case riscv_instr_name_t.ROLW: return toubvec!3(0b001);
case riscv_instr_name_t.ROR: return toubvec!3(0b101);
case riscv_instr_name_t.RORW: return toubvec!3(0b101);
case riscv_instr_name_t.RORI: return toubvec!3(0b101);
case riscv_instr_name_t.RORIW: return toubvec!3(0b101);
case riscv_instr_name_t.SEXT_B: return toubvec!3(0b001);
case riscv_instr_name_t.SEXT_H: return toubvec!3(0b001);
case riscv_instr_name_t.XNOR: return toubvec!3(0b100);
case riscv_instr_name_t.ZEXT_H: return toubvec!3(0b100);
case riscv_instr_name_t.ANDN: return UBVEC!(3, 0b111);
case riscv_instr_name_t.CLZ: return UBVEC!(3, 0b001);
case riscv_instr_name_t.CLZW: return UBVEC!(3, 0b001);
case riscv_instr_name_t.CPOP: return UBVEC!(3, 0b001);
case riscv_instr_name_t.CPOPW: return UBVEC!(3, 0b001);
case riscv_instr_name_t.CTZ: return UBVEC!(3, 0b001);
case riscv_instr_name_t.CTZW: return UBVEC!(3, 0b001);
case riscv_instr_name_t.MAX: return UBVEC!(3, 0b110);
case riscv_instr_name_t.MAXU: return UBVEC!(3, 0b111);
case riscv_instr_name_t.MIN: return UBVEC!(3, 0b100);
case riscv_instr_name_t.MINU: return UBVEC!(3, 0b101);
case riscv_instr_name_t.ORC_B: return UBVEC!(3, 0b101);
case riscv_instr_name_t.ORN: return UBVEC!(3, 0b110);
case riscv_instr_name_t.REV8: return UBVEC!(3, 0b101);
case riscv_instr_name_t.ROL: return UBVEC!(3, 0b001);
case riscv_instr_name_t.ROLW: return UBVEC!(3, 0b001);
case riscv_instr_name_t.ROR: return UBVEC!(3, 0b101);
case riscv_instr_name_t.RORW: return UBVEC!(3, 0b101);
case riscv_instr_name_t.RORI: return UBVEC!(3, 0b101);
case riscv_instr_name_t.RORIW: return UBVEC!(3, 0b101);
case riscv_instr_name_t.SEXT_B: return UBVEC!(3, 0b001);
case riscv_instr_name_t.SEXT_H: return UBVEC!(3, 0b001);
case riscv_instr_name_t.XNOR: return UBVEC!(3, 0b100);
case riscv_instr_name_t.ZEXT_H: return UBVEC!(3, 0b100);
default: return super.get_func3();
}
}

ubvec!5 get_func5() {
switch (instr_name) {
case riscv_instr_name_t.CLZ: return toubvec!5(0b0_0000);
case riscv_instr_name_t.CLZW: return toubvec!5(0b0_0000);
case riscv_instr_name_t.CPOP: return toubvec!5(0b0_0010);
case riscv_instr_name_t.CPOPW: return toubvec!5(0b0_0010);
case riscv_instr_name_t.CTZ: return toubvec!5(0b0_0001);
case riscv_instr_name_t.CTZW: return toubvec!5(0b0_0001);
case riscv_instr_name_t.ORC_B: return toubvec!5(0b0_0111);
case riscv_instr_name_t.REV8: return toubvec!5(0b1_1000);
case riscv_instr_name_t.SEXT_B: return toubvec!5(0b0_0100);
case riscv_instr_name_t.SEXT_H: return toubvec!5(0b0_0101);
case riscv_instr_name_t.CLZ: return UBVEC!(5, 0b0_0000);
case riscv_instr_name_t.CLZW: return UBVEC!(5, 0b0_0000);
case riscv_instr_name_t.CPOP: return UBVEC!(5, 0b0_0010);
case riscv_instr_name_t.CPOPW: return UBVEC!(5, 0b0_0010);
case riscv_instr_name_t.CTZ: return UBVEC!(5, 0b0_0001);
case riscv_instr_name_t.CTZW: return UBVEC!(5, 0b0_0001);
case riscv_instr_name_t.ORC_B: return UBVEC!(5, 0b0_0111);
case riscv_instr_name_t.REV8: return UBVEC!(5, 0b1_1000);
case riscv_instr_name_t.SEXT_B: return UBVEC!(5, 0b0_0100);
case riscv_instr_name_t.SEXT_H: return UBVEC!(5, 0b0_0101);
default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
assert (false);
}
}

override ubvec!7 get_func7() {
switch (instr_name) {
case riscv_instr_name_t.ANDN: return toubvec!7(0b010_0000);
case riscv_instr_name_t.CLZ: return toubvec!7(0b011_0000);
case riscv_instr_name_t.CLZW: return toubvec!7(0b011_0000);
case riscv_instr_name_t.CPOP: return toubvec!7(0b011_0000);
case riscv_instr_name_t.CPOPW: return toubvec!7(0b011_0000);
case riscv_instr_name_t.CTZ: return toubvec!7(0b011_0000);
case riscv_instr_name_t.CTZW: return toubvec!7(0b011_0000);
case riscv_instr_name_t.MAX: return toubvec!7(0b000_0101);
case riscv_instr_name_t.MAXU: return toubvec!7(0b000_0101);
case riscv_instr_name_t.MIN: return toubvec!7(0b000_0101);
case riscv_instr_name_t.MINU: return toubvec!7(0b000_0101);
case riscv_instr_name_t.ORC_B: return toubvec!7(0b001_0100);
case riscv_instr_name_t.ORN: return toubvec!7(0b010_0000);
case riscv_instr_name_t.ANDN: return UBVEC!(7, 0b010_0000);
case riscv_instr_name_t.CLZ: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.CLZW: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.CPOP: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.CPOPW: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.CTZ: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.CTZW: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.MAX: return UBVEC!(7, 0b000_0101);
case riscv_instr_name_t.MAXU: return UBVEC!(7, 0b000_0101);
case riscv_instr_name_t.MIN: return UBVEC!(7, 0b000_0101);
case riscv_instr_name_t.MINU: return UBVEC!(7, 0b000_0101);
case riscv_instr_name_t.ORC_B: return UBVEC!(7, 0b001_0100);
case riscv_instr_name_t.ORN: return UBVEC!(7, 0b010_0000);
case riscv_instr_name_t.REV8:
return toubvec!7(0b011_0100 | toubvec!7(is_rv64())); // 0110101 64 bit
case riscv_instr_name_t.ROL: return toubvec!7(0b011_0000);
case riscv_instr_name_t.ROLW: return toubvec!7(0b011_0000);
case riscv_instr_name_t.ROR: return toubvec!7(0b011_0000);
case riscv_instr_name_t.RORW: return toubvec!7(0b011_0000);
case riscv_instr_name_t.RORI: return toubvec!7(0b011_0000);
case riscv_instr_name_t.RORIW: return toubvec!7(0b011_0000);
case riscv_instr_name_t.SEXT_B: return toubvec!7(0b011_0000);
case riscv_instr_name_t.SEXT_H: return toubvec!7(0b011_0000);
case riscv_instr_name_t.XNOR: return toubvec!7(0b010_0000);
case riscv_instr_name_t.ZEXT_H: return toubvec!7(0b000_0100);
return (UBVEC!(7, 0b011_0100) | toubvec!7(is_rv64())); // 0110101 64 bit
case riscv_instr_name_t.ROL: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.ROLW: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.ROR: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.RORW: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.RORI: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.RORIW: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.SEXT_B: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.SEXT_H: return UBVEC!(7, 0b011_0000);
case riscv_instr_name_t.XNOR: return UBVEC!(7, 0b010_0000);
case riscv_instr_name_t.ZEXT_H: return UBVEC!(7, 0b000_0100);
default: return super.get_func7();
}
}
Expand Down
16 changes: 8 additions & 8 deletions euvm/riscv/gen/isa/riscv_zbc_instr.d
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ import riscv.gen.target: supported_isa;

import std.format: format;

import esdl.data.bvec: ubvec, toubvec, clog2;
import esdl.data.bvec: ubvec, UBVEC, clog2;
import uvm;

import std.algorithm: canFind;
Expand All @@ -45,25 +45,25 @@ class riscv_zbc_instr: riscv_instr
switch (instr_name) {
case riscv_instr_name_t.CLMUL,
riscv_instr_name_t.CLMULH,
riscv_instr_name_t.CLMULR: return toubvec!7(0b011_0011);
riscv_instr_name_t.CLMULR: return UBVEC!(7, 0b011_0011);
default: return super.get_opcode();
}
}

override ubvec!3 get_func3() {
switch (instr_name) {
case riscv_instr_name_t.CLMUL: return toubvec!3(0b001);
case riscv_instr_name_t.CLMULH: return toubvec!3(0b011);
case riscv_instr_name_t.CLMULR: return toubvec!3(0b010);
case riscv_instr_name_t.CLMUL: return UBVEC!(3, 0b001);
case riscv_instr_name_t.CLMULH: return UBVEC!(3, 0b011);
case riscv_instr_name_t.CLMULR: return UBVEC!(3, 0b010);
default: return super.get_func3();
}
}

override ubvec!7 get_func7() {
switch (instr_name) {
case riscv_instr_name_t.CLMUL: return toubvec!7(0b000_0101);
case riscv_instr_name_t.CLMULH: return toubvec!7(0b000_0101);
case riscv_instr_name_t.CLMULR: return toubvec!7(0b000_0101);
case riscv_instr_name_t.CLMUL: return UBVEC!(7, 0b000_0101);
case riscv_instr_name_t.CLMULH: return UBVEC!(7, 0b000_0101);
case riscv_instr_name_t.CLMULR: return UBVEC!(7, 0b000_0101);
default: return super.get_func7();
}
}
Expand Down
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