AKER: Safe and Secure SoC Access Control

Abstract:

The growing popularity of modular system-on-chip (SoC) architectures presents an increas- ing need for defense against sensitive data access from malicious hardware. In security-critical applications, IP cores have different privilege levels for accessing shared resources, which must be regulated by an access control system. AKER is an existing high-performance modular access control framework for AMBA AXI4 on-chip interconnects. We are developing an adap- tation of AKER onto network-on-chip (NoC) applications to form a high-bandwidth access control wrapper (ACW). Our adaptation is to be implemented onto ESP, an open-source rapid SoC development platform created by the University of Columbia. We have successfully set up the ESP project, and integrate a simplified AKER access control module into the project.

Team Members:

• Hosein Yavarzadeh
• Brandon Erickson
• Chi Chow

Reports and Presentation Slides:

You can find our reports and presentation slides under Reports and Presentations folders respectively in this repository.

Publications

Overview paper:

AKER: A Design and Verification Framework for Safe and Secure SoC Access Control (Francesco Restuccia, Andres Meza, and Ryan Kastner)

The ESP website contains the most up-to-date information on the ESP project. The Documentation page contains detailed guides and video tutorials that will be released periodically to help users get the most out of ESP.

ESP is an open-source platform for heterogeneous SoC design and prototype on FPGA. It provides a flexible tile-based architecture built on a multi-plane network-on-chip.

In addition to the architecture, ESP provides users with templates and scripts to create new accelerators from SystemC, Chisel, and C/C++. The ESP design methodology eases the process of integrating processors and accelerators into an SoC by offering platform services, such as DMA, distributed interrupt, and run-time coherence selection, that hide the complexity of hardware and software integration from the accelerator designer.

Currently, ESP supports the integration of multi-core LEON3 processor from GRLIB and single-core Ariane processors from the Pulp Platform. LEON3 implements the SPARC V8 32-bits ISA, while Ariane implements the RISC-V 64-bits ISA.

In addition to processor cores, ESP embeds accelerator design examples created with Stratus HLS in SystemC, Vivado HLS in C/C++ and Chisel.

Furthermore, ESP can serve as a platform to integrate third-party IP blocks. For example, ESP integrates the NVIDIA Deep Learning Accelerator NVDLA, which can be placed on any ESP accelerator tile.

Publications

Overview paper:

Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni. "Agile SoC Development with Open ESP." IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020.

The Publications page of the ESP website contains the complete list of publications related to ESP.

Repository organization

Here is a brief description of the main directories in the repository, please refer to the READMEs inside each of them for more information.

• accelerators contains multiple accelerator design and integration flows, as well as many example accelerators.

• constraints contains the constraints and attributes for each supported FPGA board (or ASIC technology).

• socs contains the working folders for launching all Make targets. There is one working folder for each supported FPGA board (or ASIC technology).

• rtl contains the whole RTL code base, excluding the accelerators RTL and the RTL generated in the working folder by the SoCGen and SocketGen tools.

• soft contains bootloader, Linux kernel and root file system, and bare-metal library for each of the available processor cores. It also contains bare-metal, user space and kernel space libraries for invoking and managing accelerators.

• tech is the destination of the RTL generated by the HLS-based and Chisel-based accelerator design flows. It is also the destination of the RTL generated with HLS for the SystemC implementation of the cache hierarchy. The generated RTL is organized based on the target FPGA (or ASIC) technology.

• tools contains tools for design automation and for communicating with an ESP SoC from a host machine.

• utils contains various scripts and utilities, including the main Makefiles, the RTL file lists, and the software toolchains installation scripts.

• .cache caches some compiled libraries so they only need to be compiled once (e.g. Xilinx simulation libraries).