add instruction

edg-l · Sep 5, 2024 · d0b3604 · d0b3604
1 parent 6495bca
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diff --git a/README.md b/README.md
@@ -8,3 +8,11 @@
 A RISC-V emulator made in Rust.
 
 Work in progress.
+
+Extensions implemented:
+
+- RV32I
+- RV64I
+- Ziscr
+- Zicntr
+- Zicond
diff --git a/src/cpu.rs b/src/cpu.rs
@@ -304,6 +304,24 @@ impl Cpu {
                         debug!("SLTU");
                         self.regs[rd] = (self.regs[rs1] < self.regs[rs2]) as u64
                     }
+                    (0x5, 0x7) => {
+                        debug!("CZERO.EQZ");
+
+                        if self.regs[rs2] == 0 {
+                            self.regs[rd] = 0;
+                        } else {
+                            self.regs[rd] = self.regs[rs1];
+                        }
+                    }
+                    (0x7, 0x7) => {
+                        debug!("CZERO.NEZ");
+
+                        if self.regs[rs2] != 0 {
+                            self.regs[rd] = 0;
+                        } else {
+                            self.regs[rd] = self.regs[rs1];
+                        }
+                    }
                     _ => Err(())?,
                 }
             }