progress and tests

Cargo.toml

@@ -6,3 +6,6 @@ edition = "2021"
 [dependencies]
 tracing = "0.1.40"
 tracing-subscriber = { version = "0.3.18", features = ["env-filter"] }
+
+[dev-dependencies]
+rstest = "0.22.0"

Makefile

@@ -4,7 +4,11 @@ SRCS = $(wildcard tests/*.s)
 
 PROGS = $(patsubst %.s,%.bin,$(SRCS))
 
-all: $(PROGS)
+.PHONY: test
+test: test_files
+	cargo t
+
+test_files: $(PROGS)
 
 %.bin: %.s
 	riscv64-unknown-elf-gcc -Wl,-Ttext=0x0 -nostdlib -o $@ $<

src/bus.rs

@@ -1,3 +1,5 @@
+use tracing::{debug, instrument};
+
 use crate::dram::Dram;
 
 /// The address which dram starts, same as QEMU virt machine.
@@ -9,14 +11,18 @@ pub struct Bus {
 }
 
 impl Bus {
+    #[instrument(skip(self))]
     pub fn load(&self, addr: u64, size: u64) -> Result<u64, ()> {
+        debug!("load");
         if DRAM_BASE <= addr {
             return self.dram.load(addr, size);
         }
         Err(())
     }
 
+    #[instrument(skip(self))]
     pub fn store(&mut self, addr: u64, size: u64, value: u64) -> Result<(), ()> {
+        debug!("store");
         if DRAM_BASE <= addr {
             return self.dram.store(addr, size, value);
         }

src/cpu.rs

@@ -17,12 +17,12 @@ pub struct Cpu {
     pub csrs: [u64; 4096],
 }
 
-const MIP: usize = 0x344;
-const MIE: usize = 0x304;
-const SIP: usize = 0x144;
-const SIE: usize = 0x104;
-const MEDELEG: usize = 0x302;
-const MIDELEG: usize = 0x303;
+pub const MIP: usize = 0x344;
+pub const MIE: usize = 0x304;
+pub const SIP: usize = 0x144;
+pub const SIE: usize = 0x104;
+pub const MEDELEG: usize = 0x302;
+pub const MIDELEG: usize = 0x303;
 
 impl Cpu {
     pub fn new(code: Vec<u8>) -> Self {
@@ -51,6 +51,8 @@ impl Cpu {
                 break;
             }
 
+            self.regs[0] = 0;
+
             // This is a workaround for avoiding an infinite loop.
             if self.pc == 0 {
                 break;
@@ -60,14 +62,18 @@ impl Cpu {
         Ok(())
     }
 
+    #[instrument(skip(self))]
     fn load_csr(&self, addr: usize) -> u64 {
+        debug!("loading csr");
         match addr {
             SIE => self.csrs[MIE] & self.csrs[MIDELEG],
             _ => self.csrs[addr],
         }
     }
 
+    #[instrument(skip(self))]
     fn store_csr(&mut self, addr: usize, value: u64) {
+        debug!("storing csr");
         match addr {
             SIE => {
                 self.csrs[MIE] =

src/dram.rs

@@ -4,7 +4,7 @@ pub const DRAM_SIZE: u64 = 1024 * 1024 * 128; // 128MiB
 
 #[derive(Debug, Clone)]
 pub struct Dram {
-    dram: Vec<u8>,
+    pub dram: Vec<u8>,
 }
 
 impl Dram {

src/lib.rs

@@ -0,0 +1,3 @@
+pub mod bus;
+pub mod cpu;
+pub mod dram;