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Guard clock gating cell #3

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Guard clock gating cell #3

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5df6ff1
Guard clock gating cell
M0stafaRady Sep 24, 2024
6dc2a37
gate the clock in case no clock gate enable
M0stafaRady Sep 24, 2024
6685e0f
Add general cell source code at ip_untilities https://github.com/efab…
M0stafaRady Sep 30, 2024
f48ebb2
Add semicolon
M0stafaRady Sep 30, 2024
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29 changes: 13 additions & 16 deletions scripts/bus_wrap.py
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Original file line number Diff line number Diff line change
Expand Up @@ -196,22 +196,19 @@ def print_wires(bus_type):

# print the clock gating cell
clkgatecell = f"""
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];

(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
`endif
.GCLK(clk_g),
.GATE(clk_gated_en),
.CLK({clk_net})
);
"""
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk({clk_net}),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);
"""
print(clkgatecell)
# Print clock wire declaration
print(f"\twire\t\t{IP['clock']['name']} = clk_g;") #{clk_net};")
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