regenerate apb wrapper to have gated clock and update fw

efabless · Jul 8, 2024 · f1fca7b · f1fca7b
1 parent 1596c2e
commit f1fca7b
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Showing 6 changed files with 67 additions and 8 deletions.
diff --git a/EF_GPIO8.yaml b/EF_GPIO8.yaml
@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.0.5
-  date: 20-5-2024
+  version: v1.0.6
+  date: 08-07-2024
   category: digital
   tags:
     - peripheral

diff --git a/fw/EF_GPIO8.c b/fw/EF_GPIO8.c
@@ -3,6 +3,10 @@
 
 #include <EF_GPIO8.h>
 
+void EF_GPIO_setGclkEnable (uint32_t gpio_base, int value){
+    EF_GPIO8_TYPE* gpio = (EF_GPIO8_TYPE*)gpio_base;
+    gpio->GCLK = value;
+}
 
 // inline int GPIO_readData(enum port_types port) __attribute__((always_inline));
 int EF_GPIO8_readData(uint32_t gpio_base){

diff --git a/fw/EF_GPIO8.h b/fw/EF_GPIO8.h
@@ -12,6 +12,9 @@
 #define GPIO8_INPUT 0
 #define GPIO8_OUTPUT 1
 
+void EF_GPIO_setGclkEnable (uint32_t gpio_base, int value);
+
+
 //! reads the input value of the GPIOs
     /*!
       \param gpio_base The base memory address of GPIO registers.

diff --git a/fw/EF_GPIO8_regs.h b/fw/EF_GPIO8_regs.h
@@ -70,6 +70,7 @@ typedef struct _EF_GPIO8_TYPE_ {
 	__R 	MIS;
 	__R 	RIS;
 	__W 	IC;
+	__W 	GCLK;
 } EF_GPIO8_TYPE;
 
 #endif

diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.pp.v
@@ -22,8 +22,11 @@
 `timescale			1ns/1ps
 `default_nettype	none
 
-
 module EF_GPIO8_APB (
+`ifdef USE_POWER_PINS 
+	input wire VPWR,
+	input wire VGND,
+`endif 
 	input wire          PCLK,
                                         input wire          PRESETn,
                                         input wire          PWRITE,
@@ -35,9 +38,9 @@ module EF_GPIO8_APB (
                                         output wire [31:0]  PRDATA,
                                         output wire         IRQ
 ,
-input	wire	[8-1:0]	io_in,
-output	wire	[8-1:0]	io_out,
-output	wire	[8-1:0]	io_oe
+	input	wire	[8-1:0]	io_in,
+	output	wire	[8-1:0]	io_out,
+	output	wire	[8-1:0]	io_oe
 );
 
 	localparam	DATAI_REG_OFFSET = 16'h0000;
@@ -47,7 +50,23 @@ output	wire	[8-1:0]	io_oe
 	localparam	MIS_REG_OFFSET = 16'hFF04;
 	localparam	RIS_REG_OFFSET = 16'hFF08;
 	localparam	IC_REG_OFFSET = 16'hFF0C;
-	wire		clk = PCLK;
+
+        wire clk_g;
+        wire clk_gated_en = GCLK_REG[0];
+
+    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+	`ifdef USE_POWER_PINS 
+        .VPWR(VPWR), 
+        .VGND(VGND), 
+        .VNB(VGND),
+		.VPB(VPWR),
+    `endif
+        .GCLK(clk_g), 
+        .GATE(clk_gated_en), 
+        .CLK(PCLK)
+        );
+
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;
 
 
@@ -107,6 +126,12 @@ output	wire	[8-1:0]	io_oe
                                         else if(apb_we & (PADDR[16-1:0]==DIR_REG_OFFSET))
                                             DIR_REG <= PWDATA[8-1:0];
 
+	localparam	GCLK_REG_OFFSET = 16'hFF10;
+	reg [0:0] GCLK_REG;
+	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
+                                        else if(apb_we & (PADDR[16-1:0]==GCLK_REG_OFFSET))
+                                            GCLK_REG <= PWDATA[1-1:0];
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
@@ -308,6 +333,7 @@ output	wire	[8-1:0]	io_oe
 			(PADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(PADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(PADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(PADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	PREADY = 1'b1;

diff --git a/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v b/hdl/rtl/bus_wrappers/EF_GPIO8_APB.v
@@ -27,6 +27,10 @@
 `include			"apb_wrapper.vh"
 
 module EF_GPIO8_APB (
+`ifdef USE_POWER_PINS
+	input wire VPWR,
+	input wire VGND,
+`endif
 	`APB_SLAVE_PORTS,
 	input	wire	[8-1:0]	io_in,
 	output	wire	[8-1:0]	io_out,
@@ -40,7 +44,23 @@ module EF_GPIO8_APB (
 	localparam	MIS_REG_OFFSET = `APB_AW'hFF04;
 	localparam	RIS_REG_OFFSET = `APB_AW'hFF08;
 	localparam	IC_REG_OFFSET = `APB_AW'hFF0C;
-	wire		clk = PCLK;
+
+        wire clk_g;
+        wire clk_gated_en = GCLK_REG[0];
+
+    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+    `ifdef USE_POWER_PINS 
+        .VPWR(VPWR), 
+        .VGND(VGND), 
+        .VNB(VGND),
+		.VPB(VPWR),
+    `endif 
+        .GCLK(clk_g), 
+        .GATE(clk_gated_en), 
+        .CLK(PCLK)
+        );
+
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;
 
 
@@ -94,6 +114,10 @@ module EF_GPIO8_APB (
 	assign	bus_oe = DIR_REG;
 	`APB_REG(DIR_REG, 0, 8)
 
+	localparam	GCLK_REG_OFFSET = `APB_AW'hFF10;
+	reg [0:0] GCLK_REG;
+	`APB_REG(GCLK_REG, 0, 1)
+
 	reg [31:0] IM_REG;
 	reg [31:0] IC_REG;
 	reg [31:0] RIS_REG;
@@ -289,6 +313,7 @@ module EF_GPIO8_APB (
 			(PADDR[`APB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(PADDR[`APB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(PADDR[`APB_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	PREADY = 1'b1;