Merge pull request #81 from mole99/netlist-gen

Improve netlist generation

Changelog.md

@@ -1,3 +1,10 @@
+# 2.3.5
+
+## Common
+
+- Improve netlist generation
+    * Schematic netlist is always generated to get the correct port order for the extracted netlists
+
 # 2.3.4
 
 ## Common

cace/__version__.py

@@ -11,7 +11,7 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
-__version__ = '2.3.4'
+__version__ = '2.3.5'
 
 if __name__ == '__main__':
     print(__version__, end='')

cace/cace_cli.py

@@ -112,7 +112,7 @@ def cli():
         '-s',
         '--source',
         type=str,
-        choices=['schematic', 'layout', 'rcx', 'all', 'best'],
+        choices=['schematic', 'layout', 'pex', 'rcx', 'best'],
         default='best',
         help="""choose the netlist source for characterization. By default, or when using \'best\', characterization is run on the full R-C
     parasitic extracted netlist if the layout is available, else on the schematic captured netlist.""",

cace/common/cace_makeplot.py

@@ -45,7 +45,7 @@
 from ..logging import debug as dbg
 
 
-def cace_makeplot(dsheet, param, plotdir, parent=None):
+def cace_makeplot(dsheet, param, plotdir=None, parent=None):
     """
     Given a plot record from a spec sheet and a full set of testbenches, generate
     a plot.  The name of the plot file and the vectors to plot, labels, legends,
@@ -583,7 +583,7 @@ def cace_makeplot(dsheet, param, plotdir, parent=None):
     if legend:
         legend.set_draggable(True)
 
-    if parent == None:
+    if plotdir:
         paths = dsheet['paths']
         """if 'plots' in paths:
             plotdir = paths['plots']

cace/common/cace_regenerate.py

@@ -1225,42 +1225,31 @@ def regenerate_netlists(dsheet):
     runtime_options = dsheet['runtime_options']
     source = runtime_options['netlist_source']
 
-    # PEX (parasitic capacitance-only) netlists are generated only by request.
+    # Always generate the schematic netlist
+    # Either the netlist source is "schematic", or we need it
+    # to get the correct port order for the extracted netlists
+    result = regenerate_schematic_netlist(dsheet)
+
+    # Layout extracted netlist
+    if source == 'layout':
+        result = regenerate_lvs_netlist(dsheet)
+        return result
+
+    # PEX (parasitic capacitance-only) netlist
     if source == 'pex':
         result = regenerate_lvs_netlist(dsheet, pex=True)
+
         # Also make sure LVS netlist is generated, in case LVS is run
         regenerate_lvs_netlist(dsheet)
-        regenerate_schematic_netlist(dsheet)
         return result
 
+    # RCX (R-C-extraction) netlist
     if source == 'all' or source == 'rcx' or source == 'best':
         result = regenerate_rcx_netlist(dsheet)
 
-    made_lvs_netlist = False
-    if (
-        source == 'all'
-        or source == 'layout'
-        or (source == 'best' and result == False)
-    ):
-        made_lvs_netlist = True
-        result = regenerate_lvs_netlist(dsheet)
-
-    made_schem_netlist = False
-    if (
-        source == 'all'
-        or source == 'schematic'
-        or (source == 'best' and result == False)
-    ):
-        made_schem_netlist = True
-        result = regenerate_schematic_netlist(dsheet)
-
-    # If LVS is run while netlist source is RCX, then the LVS netlist should
-    # also be generated.
-    if source == 'rcx':
-        if not made_lvs_netlist:
-            regenerate_lvs_netlist(dsheet)
-        if not made_schem_netlist:
-            regenerate_schematic_netlist(dsheet)
+        # Also make sure LVS netlist is generated, in case LVS is run
+        regenerate_lvs_netlist(dsheet)
+        return result
 
     return result