Correct user_id bit order in gl verilog and layout. #10
Workflow file for this run
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name: Block PR | |
on: | |
pull_request: | |
branches: | |
- main | |
jobs: | |
changed_files: | |
runs-on: ubuntu-latest | |
name: Test changed-files | |
permissions: | |
pull-requests: read | |
steps: | |
- name: Get changed files | |
id: changed-files | |
uses: tj-actions/changed-files@v39 | |
- name: List all changed files | |
run: | | |
for file in ${{ steps.changed-files.outputs.all_changed_files }}; do | |
echo "$file was changed" | |
if [[ "$file" == *"verilog/rtl/"* || "$file" == *"mag/"* || "$file" == *"gds/"* ]]; then | |
exit 1 | |
fi | |
done |