fixes for RTL testbenches with mgmt core wrapper

efabless · Dec 5, 2021 · 619163a · 619163a
1 parent 3246e64
commit 619163a
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Showing 2 changed files with 5 additions and 1 deletion.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
@@ -1,4 +1,6 @@
-// `default_nettype none
+ `ifdef SIM
+ `default_nettype wire
+ `endif
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");

diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
@@ -17,8 +17,10 @@
 // Digital PLL (ring oscillator + controller)
 // Technically this is a frequency locked loop, not a phase locked loop.
 
+`ifndef SIM
 `include "digital_pll_controller.v"
 `include "ring_osc2x13.v"
+`endif
 
 module digital_pll(
 `ifdef USE_POWER_PINS