Modified simple_por.v RTL to avoid the wire declaration that "cvc"

doesn't like (even though it's perfectly legal).

verilog/rtl/simple_por.v

@@ -28,7 +28,7 @@ module simple_por(
     output por_l
 );
 
-    wire mid, porb_h;
+    wire mid;
     reg inode;
 
     // This is a behavioral model!  Actual circuit is a resitor dumping