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Correct user_id bit order in gl verilog and layout. #518

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merged 2 commits into from
Jan 10, 2024
Merged

Correct user_id bit order in gl verilog and layout. #518

merged 2 commits into from
Jan 10, 2024

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d-m-bailey
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d-m-bailey commented Dec 6, 2023 •
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Note: These changes have not been tested in simulation. However, I did verify the expected change in the gl verilog. Also verified that there were changes in the mag file, but have not checked the connectivity.
However, should be the same as gf180mcu version.

Fixes #516

RTimothyEdwards
RTimothyEdwards approved these changes Dec 6, 2023
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Looks good to me. I'll close my own PR since it was missing one of the fixed lines.

@RTimothyEdwards RTimothyEdwards mentioned this pull request Dec 6, 2023
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@RTimothyEdwards RTimothyEdwards linked an issue Dec 6, 2023 that may be closed by this pull request
mpw-9: user id bits reversed in gl verilog and layout. #516
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@RTimothyEdwards RTimothyEdwards added the error Something isn't working label Dec 6, 2023
@jeffdi jeffdi merged commit cd263ed into efabless:main Jan 10, 2024
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@RTimothyEdwards RTimothyEdwards RTimothyEdwards approved these changes

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mpw-9: user id bits reversed in gl verilog and layout.
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@d-m-bailey @RTimothyEdwards @jeffdi