Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Removing non-inclusive language #325

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

Removing non-inclusive language #325

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions verilog/dv/wb_port/wb_port.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@
#include <defs.h>
#include <stub.c>

#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
#define reg_mprj_secondary (*(volatile uint32_t*)0x30000000)

/*
Wishbone Test:
Expand Down Expand Up @@ -82,9 +82,9 @@ void main()
// Flag start of the test
reg_mprj_datal = 0xAB600000;

reg_mprj_slave = 0x00002710;
reg_mprj_secondary = 0x00002710;
reg_mprj_datal = 0xAB610000;
if (reg_mprj_slave == 0x2B3D) {
if (reg_mprj_secondary == 0x2B3D) {
reg_mprj_datal = 0xAB610000;
}
}
2 changes: 1 addition & 1 deletion verilog/rtl/user_proj_example.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ module user_proj_example #(
inout vssd1, // User area 1 digital ground
`endif

// Wishbone Slave ports (WB MI A)
// Wishbone Secondary ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
Expand Down
4 changes: 2 additions & 2 deletions verilog/rtl/user_project_wrapper.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ module user_project_wrapper #(
inout vssd2, // User area 2 digital ground
`endif

// Wishbone Slave ports (WB MI A)
// Wishbone Secondary ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
Expand Down Expand Up @@ -91,7 +91,7 @@ user_proj_example mprj (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),

// MGMT SoC Wishbone Slave
// MGMT SoC Wishbone Secondary

.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
Expand Down