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1. DPRAM-Design-and-UVM-based-Verification DPRAM-Design-and-UVM-based-Verification Public

   RTL design for a DUAL-PORT RAM and a UVM based testbench for functional verification. This project was undertaken to gain familiarity with UVM constructs.

   SystemVerilog 5

2. Electronic-Ticket-Vending-Machine Electronic-Ticket-Vending-Machine Public

   This is a design for an electronic vending machine and a verilog based simulation testbench for its verification.

   Verilog

3. verilog-file-parser verilog-file-parser Public

   This automated script will parse through a verilog file RTL code and identify the module, its ports and parametrs. The path to the file should be given as an arguement on the command line, the resu…

   Python 1