🩹 Fix regexes and memory leaks

[Thomaltarix]

I fixed the parsing regexes so that this type of files can pass:

# Basic wire, direct link true to output.
#
# TRUE ---> OUTPUT

.chipsets:
                    input                   input1                  #b  o       njou        r
clock clock1

.links:
             input1     :     1        input1 :      1                      #helloworl d

And i also fixed all the memory leaks of the project.
It mostly consisted in deleting maps in the classes.

[RenardFute]

You sure "input1 : 1" should pass ?

[Thomaltarix]

I think so 👍